Documentation Discrepancy: i.MX RT700 Vector Table Mapping (RM Table 47 vs SRM Table 79)

[prathamvora]

Hi NXP Team,
I would like to report a critical discrepancy between the i.MX RT700 Reference Manual (RM) and the Security Reference Manual (SRM) regarding the Image Header overlay on the Cortex-M33 vector table.
The Discrepancy:

• Reference Manual (Table 47): Correctlly identifies offset 0x34 as the imageExecutionAddress, which is used by the Boot ROM to determine XIP vs. Load-to-RAM execution.
• Security Reference Manual (Table 79): Incorrectly labels offset 0x34 as the DebugMon handler. 

Supporting findings:

1.  ARM Standard: According to the Cortex-M33 Generic User Guide, the DebugMonitor exception is architecturally fixed at offset 0x30, while offset 0x34 is Reserved.
2. Internal Contradiction: Within the SRM itself, Figure 19 correctly shows the "Load Addr" at offset 0x34, but Table 79 on the following page contradicts this by listing DebugMon in that slot.
3. SDK Implementation: NXP SDK startup code follows the RM (Table 47) and SRM Figure 19, placing the load address at 0x34 to ensure the Boot ROM functions correctly.

[prathamvora]

@mayliu1 Can you please explain in the context of SRM what is the information and purpose Table 79 convey. The offset entry for it looks wrong to me. The startup code in the examples provided provides a vector table as per the table 47. Also as per the Coretx-M33 generic user guide the offsets are off. can you please have a look at the images i have shared with comparing docs. if possible can you point me to some other resources and docs to understand this better in case    if i am missing something. 

[mayliu1]

Hi @prathamvora ,

I fully understand your confusion, and thank you for bringing this to our attention.

Please feel assured that Table 47 in the RT700 RM is the correct one to refer for the RT700 chip.

The table shown in the RT700SRM (Table 79) describe the standard Cortex‑M33 NVIC vector table, which is a general ARM definition , and not RT700‑specific.

This difference may easily cause confusion for users.

To avoid further misunderstanding, I will submit an internal ticket to the relevant team to request clarification and better alignment in the documentation.

If you have any additional questions, please feel free to let me know. 

Best Regards

MayLiu

[mayliu1]

Hi @prathamvora ,

Thank you so much for your interest in our products and for using our community.

I checked the RT700RM and RT700SRM, I think there is no  discrepancy between the RT700RM and the RT700SRM.

The two tables you are comparing describe two different data structures:

For RT700RM Table 47 and RT700SRM Figure 19:

These describe the Image Header overlay inserted by the Boot ROM.
This is not the standard NVIC vector table.

For  RT700SRM Table 79：

This table describes the Cortex‑M33 NVIC vector table

They are used as different purposes:

1: Image Header :  it is Boot ROM parsing structure

2: NVIC Vector Table : it is Cortex‑M33 exception‑handling structure

Wish it helps you

Best Regards

MayLiu