xample: 47.6.5.12.1 Pulse Outputs Using Two Counters // (See Processor Expert PulseStream bean.) // This example generates six 10ms pulses, from QT1 output. // Assuming the chip is operating at 60 MHz. // // To do this, timer 3 is used to generate a clock with a period of 10ms. // // Timer 1 is used to gate these clocks and count the number of pulses that have // been generated. // void PulseStream_Init(void) { // Select IP_bus_clk/16 as the clock source for Timer 3 /* TMR3_CTRL: CM=0,PCS=0x0C,SCS=0,ONCE=0,LENGTH=1,DIR=0,COINIT=0,OUTMODE=3 */ setReg(TMR3_CTRL,0x1823); /* Set up mode */ /* TMR3_SCTRL: TCF=0,TCFIE=0,TOF=0,TOFIE=0,IEF=0,IEFIE=0,IPS=0,INPUT=0, Functional Description i.MX RT1050 Processor Reference Manual, Rev. 1, 03/2018 2726 NXP Semiconductors Capture_Mode=0,MSTR=0,EEOF=0,VAL=0,FORCE=0,OPS=0,OEN=0 */ setReg(TMR3_SCTRL,0x00); setReg(TMR3_LOAD,0x00); /* Reset load register */ setReg(TMR3_COMP1,37500); /* (16 * 37500 ) / 60e6 = 0.01 sec */ /* TMR3_CSCTRL: DBG_EN=0,FAULT=0,ALT_LOAD=0,ROC=0,TCI=0,UP=0,OFLAG=0, TCF2EN=0,TCF1EN=0,TCF2=0,TCF1=0,CL2=0,CL1=0 */ setReg(TMR3_CSCTRL,0x00); /* Set up comparator control register */ // Timer 3 output is the clock source for this timer. /* TMR1_CTRL: CM=0,PCS=7,SCS=0,ONCE=1,LENGTH=1,DIR=0,COINIT=0,OUTMODE=7 */ setReg(TMR1_CTRL,0x0E67); /* Set up mode */ /* TMR1_SCTRL: TCF=0,TCFIE=0,TOF=0,TOFIE=0,IEF=0,IEFIE=0,IPS=0,INPUT=0, Capture_Mode=0,MSTR=0,EEOF=0,VAL=0,FORCE=0,OPS=0,OEN=1 */ setReg(TMR1_SCTRL,0x01); setReg(TMR1_CNTR,0x00); /* Reset counter register */ setReg(TMR1_LOAD,0x00); /* Reset load register */ setReg(TMR1_COMP1,0x04); /* Set up compare 1 register */ // set to interrupt after the last pulse /* TMR1_CSCTRL: DBG_EN=0,FAULT=0,ALT_LOAD=0,ROC=0,TCI=0,UP=0,OFLAG=0, TCF2EN=0,TCF1EN=1,TCF2=0,TCF1=0,CL2=0,CL1=0 */ setReg(TMR1_CSCTRL,0x40); /* Set up comparator control register */ // Finally, start the counters running setReg(TMR3_CNTR,0); /* Reset counter */ setRegBitGroup(TMR3_CTRL,CM,0x01); /* Run source clock counter */ setRegBitGroup(TMR1_CTRL,CM,0x01); /* Run counter */