we are using imxqm and trying to suspend the cores and ddr, ew are using sc_pm_set_cpu_resume API to to resume cpu from lp mode, address parameter in the API .. is this the address scfw jumps when GIC interrupt is hit.
Yes, interrupts in the chip are managed through two IPs. One of the IP is the GIC-500 from ARM and Interrupt Steer controller and in this case it is linked to GIC-500 implementation from ARM.
