sample code for imx6s' EIM

[yingcaitan]

Hi ,

Could anyone provide me sample code for i.MX6 solo EIM, we want to read data from FPGA via EIM.(async mode). pls send a copy to my e-mail: tanyc@126.com

Thanks.

Tan.

[Yuri]

First, it is necessary to configure the EIM. Please refer to section 22.6 (Initialization
Information) in the i.MX6 S /DL Reference Manual. It provides examples how to initialize
the EIM.

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6SDLRM.pdf

  As for access to  a device, connected via the EIM - using standard C memcpy() function is
most suitable approach, assuming that memcpy() is highly optimized and performs ARM
instructions LDM / STM.

Have a great day,
Yuri

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[yingcaitan]

Hi Yuri,

EIM_CS0GCR1 0x31935B81

EIM_CS0GCR2 0x00000000

EIM_CS0RCR1 0x03000000

EIM_CS0RCR2 0x00000008

EIM_CS0WCR1 0x01080000

EIM_WCR 0x00000701

EIM_WIAR 0x00000010

EIM init for FPGA using. complete!

运行：busybox devmem 0x08040000，挂起等待，无法返回。

换一组rm.pdf中的参数：

// 32 bit memory

WR32('EIM_CS0GCR1,'h403304b1);

WR32('EIM_CS0RCR1,'h0f010000);

WR32('EIM_CS0RCR2,'h00000008);

WR32('EIM_CS0WCR1,'h0f040040);

也一样，运行：busybox devmem 0x0804000会导致suspend。

硬件原理图在我上一个帖子里面。Please help to find the reason, Thanks a lot.

在 2015-04-23 17:38:40，"Yuri Muhin" <admin@community.freescale.com> 写道：

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sample code for imx6s' EIM

reply from Yuri Muhin in i.MX Community - View the full discussion

First, it is necessary to configure the EIM. Please refer to section 22.6 (Initialization

Information) in the i.MX6 S /DL Reference Manual. It provides examples how to initialize

the EIM.

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6SDLRM.pdf

As for access to a device, connected via the EIM - using standard C memcpy() function is

most suitable approach, assuming that memcpy() is highly optimized and performs ARM

instructions LDM / STM.

Have a great day,

Yuri

[Yuri]

  Please look at my comments below.

1.

EIM_CSnGCR1[AUS] = 1 ; this means “Address unshifted”.
EIM_CSnGCR1[MUM] = 0 ; this means “Multiplexed Mode disable”.

Does it correspond Your schematic ?

2.
EIM_CSnGCR1[WC] = 1 ; this means “Write access burst length is continuous.”.

It would be better to clear this bit.

3.
Perhaps the problem concerns to the fact, that EIM clocks should be enabled for EIM

registers access. Please allow all clocks ("Clock is on during all modes, except STOP mode",

at least for testing)  via CCM Clock Gating Registers  (CCM_CCGRx, x =0..6).

Regards,

Yuri.