Hello and thank you for your enquiry.
First, here are my hardware details again:
I have an imx8mp-phycore-som from phytec.
I would like to use it with an embeddedArtists 1YM module for PCIe. This worked without any problems in the old kernel 5.15.71.
However, during today's measurements, I noticed that the timing was not quite as it should be. I was just lucky that it still worked reliably back then.
In the current BSP with kernel 6.6.23, I had problems implementing it in such a way that it could be used after a restart in the same way as after a complete shutdown. The problem was that after a restart, the message ‘Phy Link never came up’ appeared and I couldn't get the WiFi module to work reliably.
Over the last few days, I have been working intensively on getting everything to work with adjustments to the device tree, but I was unable to set the correct timing behaviour. I experimented with a fixed controller and tried various other things. At some point, I gave up and adapted the pci-imx6.c driver similar to kernel 5.15.71.
I just had the long-awaited breakthrough.
What I did: I added the W_DISABLE1 pin as gpio_desc *power_on_gpio to the imx6_pcie structure.
In imx6_pcie_host_init, this is set to high after the clock has been activated. If pcie PHY power up fails, it is set back to low. In the case of err_reg_disable, there is a 100 ms wait after disabling the regulator. In imx6_pcie_host_exit, power_on_gpio is also pulled low before disabling the clock. After disabling the regulator, there is another 100 ms wait. In imx6_pcie_probe, power_on_gpio is initialised and pulled low before the reset_gpio is handled.
This provides the necessary timing for the card to boot up cleanly.
Best
R.