mx6dl ddr_test write level issu

[chuanyanyin]

Hi All:

  I use my custom board to run ddr stress test v1.0.3,  The DDR3 is H5TQ2G63BFR,  tRCD=tRP=CL (ns) =  15, tRC = 52.5, tRAS = 37.5, When the CPU is MX6Q, everything is fine. When I test other board which  the CPU is MCIMX6U5DVM10AB, the WL is larger than 0x2F:

Would you like to run the write leveling calibration? (y/n)

  Please enter the MR1 value on the initilization script

  This will be re-programmed into MR1 after write leveling calibration

  Enter as a 4-digit HEX value, example 0004, then hit enter

0004 You have entered: 0x0004

Start write leveling calibration

Write leveling calibration completed

MMDC_MPWLDECTRL0 ch0 after write level cal: 0x004A004D

MMDC_MPWLDECTRL1 ch0 after write level cal: 0x003F0043

MMDC_MPWLDECTRL0 ch1 after write level cal: 0x001F0025

MMDC_MPWLDECTRL1 ch1 after write level cal: 0x0022003B

I'm sure  WALAT bit  of MMDCx_MDMISC is 1(0x021b0018 = 0x00011740) ,  The i.MX6_DDR_Stress_Test_User_Guide.pdf said

"If write-leveling delay is larger than 0x2f, it is suggested to

set the WALAT value on MMDCx_MDMISC register to 1 in

the initialization script and re-run the DDR_Stress_Tester".

Hower, the stress test can passed.

WL is larger than 0x2F , I Can't  make WL smaller than 0x2F. Can it cause any problem with MX6DL?

Original Attachment has been moved to: ddr_stress_test_for_dl.txt.zip

Original Attachment has been moved to: test.inc.txt.zip

[igorpadykov]

Hi chuanyan

yes can leave WALAT=0 after thorough board testing, however

it is recommended to set it to 1, since in rare cases, seems it may violate

DDR datasheets waveforms as explained below.

https://community.freescale.com/message/381090#381090

Best regards

igor

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[chuanyanyin]

Hi igor:

   I have let WALAT=0 already, but  the result is almost same.

0004 You have entered: 0x0004

Start write leveling calibration

Write leveling calibration completed

MMDC_MPWLDECTRL0 ch0 after write level cal: 0x003F0045

MMDC_MPWLDECTRL1 ch0 after write level cal: 0x0034003F

MMDC_MPWLDECTRL0 ch1 after write level cal: 0x00180016

MMDC_MPWLDECTRL1 ch1 after write level cal: 0x0013002A

When I put this value(I'm not sure it is correct ) into the flashheader.S, the Android System is not stable, it sometimes hung with  no logs displayed.

Has anyone run ddr test on DL board? I have heard that MX6DL is not stable as MX6Q, is it true?

[igorpadykov]

Hi chuanyan

instability may be used also by other factors, including bad power

supplies and wrong software configuration.

BTW had you applied latest GPU patches ? They are very critical for

stability:  IMX6LXPATCHRN

Please try software from DL dedicated page, for example

Demo

L3.0.35_4.1.0_DEMO_IMAGE_BSP : i.MX 6Quad, i.MX 6Dual, i.MX 6DualLite, i.MX 6Solo and i.MX 6Sololite Linux Binary Demo Files.

i.MX6DL|i.MX 6DualLite Processors|3D Graphics|Freescale

then try to build min. Linux image and check it

L3.0.35_4.1.0_ER_SOURCE_BSP : i.MX 6Quad, i.MX 6Dual, i.MX 6DualLite, i.MX 6Solo and i.MX 6Sololite Linux BSP Source Code Files.

~igor