kernel hangs @ Starting kernel ...

[sujithvasudevan]

We are building Linux image for our custom board based on sabre-sd.  Uart 2 is used as  debug uart. We are using yocto Fido to build the image , with meta-fsl-arm.  The console uart has been changed in the u-boot bootargs and also enabled pin-muxing for uart 2 in the dtb files.  Booting  stops at "starting kernel".  We also enabled CONFIG_DEBUG_LL, after which we are are getting the message "Uncompressing Linux... done, booting the kernel." Please help on the issue.  The log file is as below.

U-Boot 2015.07+fslc+g3f0c535 (Oct 16 2015 - 21:09:09 +0530)

CPU:   Freescale i.MX6Q rev1.0 at 792MHz

CPU:   Commercial temperature grade (0C to 95C)CPU:   Thermal invalid data, fuse: 0x0

- invalid sensor device

Reset cause: POR

Board: MX6-SabreSD

I2C:   ready

DRAM:  1 GiB

MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2

*** Warning - bad CRC, using default environment

PCI:   pcie phy link never came up

No panel detected: default to Hannstar-XGA

Display: Hannstar-XGA (1024x768)

In:    serial

Out:   serial

Err:   serial

Net:   Phy 1 not found

PHY reset timed out

FEC [PRIME]

Hit any key to stop autoboot:  0

switch to partitions #0, OK

mmc1 is current device

reading boot.scr

** Unable to read file boot.scr **

reading zImage

5946592 bytes read in 290 ms (19.6 MiB/s)

Booting from mmc ...

reading imx6q-sabresd-ldo.dtb

42395 bytes read in 19 ms (2.1 MiB/s)

Kernel image @ 0x12000000 [ 0x000000 - 0x5abce0 ]

## Flattened Device Tree blob at 18000000

   Booting using the fdt blob at 0x18000000

   Using Device Tree in place at 18000000, end 1800d59a

Starting kernel ...

Uncompressing Linux... done, booting the kernel.

=> printenv

baudrate=115200

boot_fdt=try

bootcmd=mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi

bootdelay=3

bootscript=echo Running bootscript from mmc ...; source

console=ttymxc1

emmcdev=2

ethact=FEC

ethaddr=00:00:aa:bb:cc:dd

ethprime=FEC

fb=0

fdt_addr=0x18000000

fdt_file=imx6q-sabresd-ldo.dtb

fdt_high=0xffffffff

image=zImage

initrd_high=0xffffffff

ip_dyn=yes

loadaddr=0x12000000

loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};

loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}

loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}

mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} ${video_args}

mmcboot=echo Booting from mmc ...; run video_args_script; run mmcargs; if test ${boot_fdt} = yes || test ${boot_fdt} = try; then if run loadfdt; then bootz ${loadaddr} - ${fdt_addr}; else if test ${boot_fdt} = try; then bootz; else echo WARN: Cannot load the DT; fi; fi; else bootz; fi;

mmcdev=1

mmcpart=1

mmcroot=/dev/mmcblk2p2 rootwait rw

netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp

netboot=echo Booting from net ...; run netargs; if test ${ip_dyn} = yes; then setenv get_cmd dhcp; else setenv get_cmd tftp; fi; ${get_cmd} ${image}; if test ${boot_fdt} = yes || test ${boot_fdt} = try; then if ${get_cmd} ${fdt_addr} ${fdt_file}; then bootz ${loadaddr} - ${fdt_addr}; else if test ${boot_fdt} = try; then bootz; else echo WARN: Cannot load the DT; fi; fi; else bootz; fi;

script=boot.scr

update_emmc_firmware=if test ${ip_dyn} = yes; then setenv get_cmd dhcp; else setenv get_cmd tftp; fi; if ${get_cmd} ${update_sd_firmware_filename}; then if mmc dev ${emmcdev} 1; then setexpr fw_sz ${filesize} / 0x200; setexpr fw_sz ${fw_sz} + 1; mmc write ${loadaddr} 0x2 ${fw_sz}; fi; fi

update_sd_firmware=if test ${ip_dyn} = yes; then setenv get_cmd dhcp; else setenv get_cmd tftp; fi; if mmc dev ${mmcdev}; then if ${get_cmd} ${update_sd_firmware_filename}; then setexpr fw_sz ${filesize} / 0x200; setexpr fw_sz ${fw_sz} + 1; mmc write ${loadaddr} 0x2 ${fw_sz}; fi; fi

video_args_hdmi=setenv video_args $video_args video=mxcfb${fb}:dev=hdmi,1280x720M@60,if=RGB24

video_args_lcd=setenv video_args $video_args video=mxcfb${fb}:dev=lcd,CLAA-WVGA,if=RGB666

video_args_lvds=setenv video_args $video_args video=mxcfb${fb}:dev=ldb,LDB-XGA,if=RGB666

video_args_script=for v in ${video_interfaces}; do run video_args_${v}; setexpr fb $fb + 1; done

video_interfaces=hdmi lvds lcd

Environment size: 2687/8188 bytes

thanks,

Sujith Vasudevan

[fabio_estevam]

Can you show us in a patch format the changes you did in the dts file?

[sujithvasudevan]

Hi Fabio,

The changes i made to configure uart is as follows

diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi

index 9cf7652..2f64a26 100644

--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi

+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi

@@ -699,6 +699,13 @@

  MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1

  >;

  };

+

+ pinctrl_uart2: uart2grp {

+ fsl,pins = <

+ MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1

+ MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1

+ >;

+ };

  pinctrl_uart5_1: uart5grp-1 {

  fsl,pins = <

@@ -899,6 +906,13 @@

  status = "okay";

};

+&uart2 {

+ pinctrl-names = "default";

+ pinctrl-0 = <&pinctrl_uart2>;

+ status = "okay";

+};

+

+

&usbh1 {

  vbus-supply = <&reg_usb_h1_vbus>;

  status = "okay";

--

regards,

sujith vasudevan

[sujithvasudevan · Accepted solution]

Hi

This Issue is solved.  There was conflict in pin mux setting of uart 2 in imx6qdl-sabresd.dtsi file.  I removed the following line

  MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000

  MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x80000000

  MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000

- MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000    /* conflicts with MX6QDL_PAD_EIM_D26__UART2_TX_DATA*/

+

  MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000

  MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000

  MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000

Thank You Igor and Fabio for all your inputs ...

warm regards,

Sujith Vasudevan

[igorpadykov]

Hi Sujith

from log: "CPU:  Freescale i.MX6Q rev1.0 at 792MHz"

seems this is old preproduction 1.0 version, not supported more.

Please look at attached Release Notes p.11:

Freescale decided to drop the preproduction TO1.1/TO1.0) chip support.

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

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[sujithvasudevan]

Thank You Igor,

I tried to boot the same image in another board. I get the same issue.  Here the CPU version is 1.2.  Please advice. 

U-Boot 2015.07+fslc+g3f0c535 (Oct 16 2015 - 21:09:09 +0530)

CPU:  Freescale i.MX6Q rev1.2 996 MHz (running at 792 MHz)

CPU:  Automotive temperature grade (-40C to 125C) at 19C

Reset cause: POR

Board: MX6-SabreSD

I2C:  ready

DRAM:  1 GiB

MMC:  FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2

*** Warning - bad CRC, using default environment

PCI:  pcie phy link never came up

No panel detected: default to Hannstar-XGA

Display: Hannstar-XGA (1024x768)

In:    serial

Out:  serial

Err:  serial

Net:  Phy 1 not found

PHY reset timed out

FEC [PRIME]

Error: FEC address not set.

Hit any key to stop autoboot:  0

switch to partitions #0, OK

mmc1 is current device

reading boot.scr

** Unable to read file boot.scr **

reading zImage

6235320 bytes read in 313 ms (19 MiB/s)

Booting from mmc ...

reading imx6q-sabresd-ldo.dtb

42395 bytes read in 19 ms (2.1 MiB/s)

Kernel image @ 0x12000000 [ 0x000000 - 0x5f24b8 ]

## Flattened Device Tree blob at 18000000

  Booting using the fdt blob at 0x18000000

  Using Device Tree in place at 18000000, end 1800d59a

Starting kernel ...

Uncompressing Linux... done, booting the kernel.

[igorpadykov]

Hi Sujith

had you modified uboot dcd header ...board/mx6sabresd/mx6dl_4x_mt41j128.cfg

with new board ddr settings obtained from ddr tester

i.MX6/7 DDR Stress Test Tool V2.20

~igor

[sujithvasudevan]

Hi Igor,

Thank you.  I was able to run DDR stress test successfully. I don't think its some issue with the DDR.  Here is the log.

============================================

        DDR Stress Test (2.2.0)

        Build: Sep 29 2015, 22:20:56

        Freescale Semiconductor, Inc.

============================================

============================================

        Chip ID

DIGPROG(0x020c8260) = 0x00630002

CHIP ID = i.MX6 Dual/Quad (0x63)

Internal Revision = TO1.2

============================================

============================================

        Boot Configuration

SRC_SBMR1(0x020d8004) = 0x08003040

SRC_SBMR2(0x020d801c) = 0x11000001

============================================

============================================

        DDR configuration

BOOT_CFG3[5-4]: 0x00, Single DDR channel.

DDR type is DDR3

Data width: 64, bank num: 8

Row size: 14, col size: 10

Chip select CSD0 is used

Density per chip select: 1024MB

============================================

DDR Stress Test Iteration 1

Current Tempareture: 31

============================================

DDR Freq: 396 MHz

t0.1: data is addr test

t0: memcpy10 SSN x64 test

t1: memcpy8 SSN x64 test

t2: byte-wise SSN x64 test

t3: memcpy11 random pattern test

t4: IRAM_to_DDRv2 test

t5: IRAM_to_DDRv1 test

t6: read noise walking ones and zeros test

DDR Freq: 413 MHz

t0.1: data is addr test

t0: memcpy10 SSN x64 test

t1: memcpy8 SSN x64 test

t2: byte-wise SSN x64 test

t3: memcpy11 random pattern test

t4: IRAM_to_DDRv2 test

t5: IRAM_to_DDRv1 test

t6: read noise walking ones and zeros test

DDR Freq: 432 MHz

t0.1: data is addr test

t0: memcpy10 SSN x64 test

t1: memcpy8 SSN x64 test

t2: byte-wise SSN x64 test

t3: memcpy11 random pattern test

t4: IRAM_to_DDRv2 test

t5: IRAM_to_DDRv1 test

t6: read noise walking ones and zeros test

DDR Freq: 452 MHz

t0.1: data is addr test

t0: memcpy10 SSN x64 test

t1: memcpy8 SSN x64 test

t2: byte-wise SSN x64 test

t3: memcpy11 random pattern test

t4: IRAM_to_DDRv2 test

t5: IRAM_to_DDRv1 test

t6: read noise walking ones and zeros test

DDR Freq: 475 MHz

t0.1: data is addr test

t0: memcpy10 SSN x64 test

t1: memcpy8 SSN x64 test

t2: byte-wise SSN x64 test

t3: memcpy11 random pattern test

t4: IRAM_to_DDRv2 test

t5: IRAM_to_DDRv1 test

t6: read noise walking ones and zeros test

DDR Freq: 500 MHz

t0.1: data is addr test

t0: memcpy10 SSN x64 test

t1: memcpy8 SSN x64 test

t2: byte-wise SSN x64 test

t3: memcpy11 random pattern test

t4: IRAM_to_DDRv2 test

t5: IRAM_to_DDRv1 test

t6: read noise walking ones and zeros test

DDR Freq: 528 MHz

t0.1: data is addr test

t0: memcpy10 SSN x64 test

t1: memcpy8 SSN x64 test

t2: byte-wise SSN x64 test

t3: memcpy11 random pattern test

t4: IRAM_to_DDRv2 test

t5: IRAM_to_DDRv1 test

t6: read noise walking ones and zeros test

DDR Freq: 532 MHz

t0.1: data is addr test

t0: memcpy10 SSN x64 test

t1: memcpy8 SSN x64 test

t2: byte-wise SSN x64 test

t3: memcpy11 random pattern test

t4: IRAM_to_DDRv2 test

t5: IRAM_to_DDRv1 test

t6: read noise walking ones and zeros test

Success: DDR Stress test completed!!!

-sujith

[igorpadykov]

Hi Sujith

I see you use community release with U-Boot 2015.07+fslc.

Please try Freescale official BSP from L3.14.28_1.0.0_iMX6QDLS_BUNDLE:

Board Support Packages (27)

L3.14.28_1.0.0_iMX6QDLS_BUNDLE (REV L3.14.28_1.0.0)

http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=RDIMX6SABREBRD&fpsp=1&tab=Design_Tool...

It uses v2014.04 as shown in attached Release Notes.

Difference between Freescale official BSP and Community releases and its support rules

is described on

Re: difference between Yocto Community BSP and Freescale BSP Release

~igor

[sujithvasudevan]

Hi Igor,

I tried uisng Freescale official BSP from L3.14.28_1.0.0_iMX6QDLS_BUNDLE. I still get the same issue.

U-Boot 2014.10+fslc+g5fd0b60 (Oct 28 2015 - 10:27:43)

CPU:   Freescale i.MX6Q rev1.0 at 792 MHz

Reset cause: POR

Board: MX6-SabreSD

I2C:   ready

DRAM:  1 GiB

MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2

*** Warning - bad CRC, using default environment

No panel detected: default to Hannstar-XGA

Display: Hannstar-XGA (1024x768)

In:    serial

Out:   serial

Err:   serial

Can't find PMIC:PFUZE100

Net:   Phy not found

PHY reset timed out

FEC [PRIME]

Hit any key to stop autoboot:  0

switch to partitions #0, OK

mmc1 is current device

reading boot.scr

** Unable to read file boot.scr **

reading zImage

5287656 bytes read in 246 ms (20.5 MiB/s)

Booting from mmc ...

reading imx6q-sabresd-ldo.dtb

47179 bytes read in 19 ms (2.4 MiB/s)

Kernel image @ 0x12000000 [ 0x000000 - 0x50aee8 ]

## Flattened Device Tree blob at 18000000

   Booting using the fdt blob at 0x18000000

   Using Device Tree in place at 18000000, end 1800e84a

Starting kernel ...

[igorpadykov]

Hi Sujith

it is not uboot from Freescale official BSP, as

it uses v2014.04 as shown in attached Release Notes.

Best regards

igor

[sujithvasudevan]

Hi Igor,

Thank you for the reply.

Can you help me with more info on the build.

The steps i followed  is as below.  Please correct me if i am wrong.

1. Downloaded fsl-L3.14.28_1.0.0_iMX6qdls_Bundle.tar

2. Untared fsl-L3.14.28_1.0.0_iMX6qdls_Bundle.tar which had two files in it fsl-yocto-3.14.28-1.0.0.tar.gz and L3.14.28_1.0.0_ga_images_MX6.tar.gz .

3. Untared fsl-yocto-3.14.28-1.0.0.tar.gz and followed steps in the document Freescale_Yocto_Project_User's_Guide.pdf 

     repo init -u git://git.freescale.com/imx/fsl-arm-yocto-bsp.git -b imx-3.14.28-1.0.0_ga

     repo sync

-sujith

[igorpadykov]

Hi Sujith

as this is new problem please create new thread for it.

Best regards

igor

[sujithvasudevan]

Thank you Igor,

I have made a seperate post for the build issues.

Can you share  more approaches to debug the issue.

-sujith vasudevan