The DTS configuration is as follows
&mu_m0{
status = "okay";
};
&mu1_m0{
status = "okay";
};
&mu2_m0{
status = "okay";
};
&vpu_encoder {
status = "okay";
compatible = "nxp,imx8qxp-b0-vpuenc";
boot-region = <&encoder_boot>;
rpc-region = <&encoder_rpc>;
reserved-region = <&encoder_reserved>;
reg-rpc-system = <0x40000000>;
resolution-max = <1920 1080>;
fps-max = <120>;
// power-domains = <&pd IMX_SC_R_VPU_ENC_0>, <&pd IMX_SC_R_VPU_ENC_1>,
// <&pd IMX_SC_R_VPU>;
// power-domain-names = "vpuenc1", "vpuenc2", "vpu";
mbox-names = "enc1_tx0", "enc1_tx1", "enc1_rx",
"enc2_tx0", "enc2_tx1", "enc2_rx";
mboxes = <&mu1_m0 0 0
&mu1_m0 0 1
&mu1_m0 1 0
&mu2_m0 0 0
&mu2_m0 0 1
&mu2_m0 1 0>;
vpu_enc_core0: core0@1020000 {
compatible = "fsl,imx8-mu1-vpu-m0";
reg = <0x1020000 0x20000>;
reg-csr = <0x1090000 0x10000>;
interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
fsl,vpu_ap_mu_id = <17>;
fw-buf-size = <0x200000>;
rpc-buf-size = <0x80000>;
print-buf-size = <0x80000>;
};
vpu_enc_core1: core1@1040000 {
compatible = "fsl,imx8-mu2-vpu-m0";
reg = <0x1040000 0x20000>;
reg-csr = <0x10A0000 0x10000>;
interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
fsl,vpu_ap_mu_id = <18>;
fw-buf-size = <0x200000>;
rpc-buf-size = <0x80000>;
print-buf-size = <0x80000>;
};
};
&vpu_decoder {
boot-region = <&decoder_boot>;
rpc-region = <&decoder_rpc>;
reg-csr = <0x2d040000>;
core_type = <1>;
status = "okay";
};