imx8mm msi-controller

[jyu1]

I am writing a driver for PCI card that consists of multiple devices, including few I2C buses. I2C buses require device-tree node to reuse existing Linux drivers.

I am having the main driver for dev@0,0 initializing PCI and bar@0 as a platform driver. dev@0,0 is enabling PCI MSI-X interrupts. Some of the interrupts are supposed to be used by bar@0.  I cannot see any msi-controller in the imx8mm device tree. Do you have a suggestion on how to specify which MSI interrupts to be used by the child nodes? Is there any other way to make shared MSI interrupts handling (using device-tree) with the imx8mm hardware?

 soc@0 {
         pcie@33800000 {
             pci@0,0 {
                 #address-cells = <0x03>;
                 bus-range = <0x01 0xff>;
                 interrupts = <0x01>;
                 interrupt-map = <0x10000 0x00 0x00 0x01 &gic GIC_SPI 0x7d IRQ_TYPE_LEVEL_HIGH 
                                  0x10000 0x00 0x00 0x02 &gic GIC_SPI 0x7c IRQ_TYPE_LEVEL_HIGH 
                                  0x10000 0x00 0x00 0x03 &gic GIC_SPI 0x7b IRQ_TYPE_LEVEL_HIGH 
                                  0x10000 0x00 0x00 0x04 &gic GIC_SPI 0x7a IRQ_TYPE_LEVEL_HIGH>;
                 #size-cells = <0x02>;
                 device_type = "pci";
                 interrupt-map-mask = <0xffff00 0x00 0x00 0x07>;
                 compatible = "pci16c3,abc", "pciclass,060400", "pciclass,0604";
                 ranges = <0x82000000 0x00 0x18000000 0x82000000 0x00 0x18000000 0x00 0x6000000>;
                 #interrupt-cells = <0x01>;
                 reg = <0x00 0x00 0x00 0x00 0x00>;

                 dev@0,0 {
                     #address-cells = <0x01>;
                     #size-cells = <0x01>;
                     interrupts = <0x01>;
                     compatible = "pci10ee,9024", "pciclass,058000", "pciclass,0580";
                     ranges = < 0x02 0x83010000 0x00 0x18000000  0x4000000
                                0x00 0x83010000 0x00 0x1c000000  0x40000>;
                     reg = <0x10000 0x00 0x00 0x00 0x00>;

                     bar@0 {
                        compatible = "simple-bus";
                        /* Map BAR 0 to address 0*/
                        ranges = <0x0 0x0 0x40000>;
                        interrupts = <0x01>;
                        #address-cells = <0x01>;
                        #size-cells = <0x01>;
                        qdma: qdma@0 {
                            compatible = "xilinx,qdma";
                            #dma-cells = <1>;
                            dma-channels = <32>;
                            interrupts = <0x01>;
                            status = "okay";
                            reg = <0x00 0x40000>;
                        };

imx8mm.dtsi nodes for gic and pcie:

        gic: interrupt-controller@38800000 {
            compatible = "arm,gic-v3";
            reg = <0x38800000 0x10000>, /* GIC Dist */
                  <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
            #interrupt-cells = <3>;
            interrupt-controller;
            interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
        };
        pcie0: pcie@33800000 {
            compatible = "fsl,imx8mm-pcie", "snps,dw-pcie";
            reg = <0x33800000 0x400000>,
                <0x1ff00000 0x80000>;
            reg-names = "dbi", "config";
            #address-cells = <3>;
            #size-cells = <2>;
            device_type = "pci";
            bus-range = <0x00 0xff>;
            ranges =  <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
                   0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
            num-lanes = <1>;
            num-viewport = <4>;
            interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "msi";
            #interrupt-cells = <1>;
            interrupt-map-mask = <0 0 0 0x7>;
            interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
                    <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
                    <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
                    <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
            linux,pci-domain = <0>;
            fsl,max-link-speed = <2>;
            power-domains = <&pcie_pd>;
            resets = <&src IMX8MQ_RESET_PCIEPHY>,
                 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
                 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>,
                 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
            reset-names = "pciephy", "apps", "clkreq", "turnoff";
            fsl,imx7d-pcie-phy = <&pcie_phy>;
        };

[joanxie]

maybe you can refer to this link

https://patchwork.kernel.org/project/linux-pci/cover/20181113225734.8026-1-marc.zyngier@arm.com/