imx8mm SPI driver

[Alex22]

Hi all,

I’m using the SPI interface in master mode from the imx8mm. I’m not so familiar how the Kernel driver will handle a transmission to an SPI slave. The Chip-Select (CS) signal to set or reset the pin takes verry long. Maybe it’s normal, but I not able to explain it. Her is what I see.

When the driver is entered and he start the transmission the function spi_write_then_read() (spi.c) will been called and this function will call function in spi-imx.c. Ok, understood, my question is.

Why dose the CS takes so long to set and reset? I’m not able to explain it or how I can fix this issue. I will send 4 Byte and read 4 Byte via the function.

Device-tree properties and anything else will not help. The 4 CPU’s do nothing else than this test code.

Thanks, for any explanation.

[Chavira]

Hi @Alex22!
Thank you for contacting NXP Support!

I made the test using Spidev and those are the results:

Please check our device tree configurations for ecspi2 on the next links:

https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi

https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/arch/arm64/boot/dts/freescale/imx8mm.dtsi

Best Regards!
Chavira

[Alex22]

Hi Chavira,

the time slice looks verry good and I would like to have the same result. Is it possible to say which slice is CS, MOSI, MISO and CLK?

I changed a little in the device tree and I'm relative sure that the behaviour is the same, but the result not. Here are the tree settings.

gpio5:gpio@30240000 {
compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
reg = <0x30240000 0x10000>;
interrupts = <0x00 0x48 0x04 0x00 0x49 0x04>;
clocks = <0x02 0xe3>;
gpio-controller;
#gpio-cells = <0x02>;
interrupt-controller;
#interrupt-cells = <0x02>;
gpio-ranges = <0x14 0x00 0x77 0x1e>;
phandle = <0x24>;
};

ecspi2grp {
fsl,pins = <0x204 0x46c 0x00 0x00 0x00 0x82 0x208 0x470 0x00 0x00 0x00 0x82 0x20c 0x474 0x00 0x00 0x00 0x82>;
phandle = <0x28>;
};

ecspi2_cs:ecspi2csgrp {
fsl,pins = <0x210 0x478 0x000 0x5 0x0 0x40000
>;
};

spi@30830000 {
compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
/*compatible = "fsl,imx8mm-ecspi\0fsl,imx51-ecspi";*/
#address-cells = <0x01>;
#size-cells = <0x00>;
reg = <0x30830000 0x10000>;
interrupts = <0x00 0x20 0x04>;
clocks = <0x02 0xa0 0x02 0xa0>;
clock-names = "ipg", "per";
dmas = <0x21 0x02 0x07 0x01 0x21 0x03 0x07 0x02>;
dma-names = "rx\0tx";
status = "okay";
pinctrl-names = "default";

fsl,spi-num-chipselects = <1>;
pinctrl-0 = <0x28 &ecspi2_cs 0x2a>;
cs-gpios = <&gpio5 0x0d 0x01>;
/*num-cs = <0x01>;*/

lan9253@0 {
compatible = "lan9253";
spi-max-frequency = <0x1312d00>;
reg = <0x00>;
};
};

Best regards,

Alex

[Chavira]

Hi @Alex22!

How are you implementing your device tree and drivers?

What BSP are you using?

I will try to use Spidev to have an SPI signals and compare it with your results.

You can consult our driver documentation in chapter 4.3 of our Linux Reference Manual.

Best Regards!
Chavira

[Alex22]

Linux imx8mm 5.10.72-spi_dbg+ #26 SMP PREEMPT_RT Thu Jan 25 12:36:32 CET 2024 aarch64 aarch64 aarch64 GNU/Linux

spi@30830000 {
compatible = "fsl,imx8mm-ecspi\0fsl,imx51-ecspi";
/*#address-cells = <0x01>;*/
/*#size-cells = <0x00>;*/
reg = <0x30830000 0x10000>;
interrupts = <0x00 0x20 0x04>;
clocks = <0x02 0xa0 0x02 0xa0>;
clock-names = "ipg\0per";
dmas = <0x21 0x02 0x07 0x01 0x21 0x03 0x07 0x02>;
dma-names = "rx\0tx";
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <0x28 0x29 0x2a>;
cs-gpios = <0x24 0x0d 0x01>;
num-cs = <0x01>;

lan9253@0 {
compatible = "microchip,lan9253";
spi-max-frequency = <0x2625A00>;
reg = <0x00>;
};
};

[Alex22]