imx8mm, Cortex-A53, Cortex-M4 MU interrupt handling clarification required.

[prasannakulkarni]

Hi, We have followed the application note, AN13201, i.MX 8M Mini Heterogenous Low Power Voice Control Solution.

Enable the MU interrupt as the wake trigger in the ATF (see gpc_common.c):
/* enable the MU wakeup */
if (imx_is_m4_enabled())
mmio_clrbits_32(IMX_GPC_BASE + gpc_imr_offset[last_core] + 0x8, BIT(24));

unable to understand this ...

IMX_GPC_BASE --> 303A_0000h

gpc_imr_offset[last_core] -->> IMR1_CORE3_A53,

The four IMRn_CORE2_A53 (n = 1,2,3,4) registers are used as interrupt mask for A53
core3.
Address: 303A_0000h base + 1D0h offset = 303A_01D0h

+0x8 is added to it so 0x303A01D8 is shifted for 24 bits and bit is clreared

Description is like this from TRM.

GPC_IMR3_CORE3_A53 field descriptions
Field
Description
IMR3_CORE3_ A53 core3 IRQ[95:64] masking bits:
A53
0 IRQ not masked
1 IRQ masked

not able to make the link bw TRM reg and its implementation. kindly clarify

We are unable to understand the mechanism given in reference manual, and this implementation... which reg's what bit is getting cleared...

[Zhiming_Liu]

Please refer  AN13400 

1.Trigger interrupt in M core, you should refer the MU(Message Unit) chapter in RM.

2.Enable SLPCR_A53_SATWAKEUP_STOP_MODE in ATF.

3.Handle interrupt in imx-mailbox kernel driver.

[prasannakulkarni]

Can we read these interrupts at user-space? is it possible?