Hello,
We have two unit, one is okay to capture, and the CLK signal is like "MIPI_CLK1.png". The other one cannot capture image normally with high probability (90%), we measure the CLK signal, the signal looks fine as "MIPI_CLK1.png". After adjusting damping resistor by our HW on the issue unit, it can capture images normally.
Are there any methods about adjusting the IMX8 setting like changing damping resistor?
Environment description: IMX8MP + TP2860 decorder + MIPI CSI + 2 lane
- Signal that cannot capture images before adjusting damping resistor on the issue unit.
- Signal that can capture images after adjusting damping resistor on issue unit, it looks shift but is workable.
HW modification is as below and attached "MIPI_hw_modify.png"
Hi @KenBCHu
The root cause should still be hardware layout.
You can try to adjust HS_RX_ TERMINATION_ IMPEDENCE bit in MIPI_CSIx_DPHY_SLAVE_CTRL_LOW register. This is a software workaround but may not solve this issue very perfectly.
Excuse me
Already referred to
i.MX 8M Plus Hardware Developer Guide, Rev. 0, 03/2021
Table 24. Trace impedance recommendations (continued)
Differential signaling, MIPI (CSI and DSI),
Almost all plagiarized
i.MX 8M Plus LPDDR4 EVK computing module design files
8MPLUSLPD4-CPU/LAY-46368_A1.brd
Waiting for nxp design requirements to design. Is there any important hardware design information or regulations that can be re-evaluated and referred to?
Hi @Zhiming_Liu,
We try to modify three type of MIPI_CSIx_DPHY_SLAVE_CTRL_LOW registers as attached patch, but it seem not work on the issue unit.
By the way, we update the issue situation and we found happened at some units. Please refer to updated post. Any suggestion from your side?
Thanks.
By the way, we update the issue situation and we found happened at some units.
-->Can you evaluate the probability of this issue with the board? Maybe it's a difference caused by the manufacturing process.