Board:imx6ul When UBOOT resets LCDIF block, what is the reason for clkgate setting failure
When the LCDIF register is normal, the status is c0000000
When the LCDIF register is abnormal, the state is 80000000
Hi 我的钱 去玩儿群无
LCD clocks are enabled in CCM_CCGR2 register described in
sect.18.6.25 CCM Clock Gating Register 2 (CCM_CCGR2)
i.MX 6UltraLite Applications Processor Reference Manual
clocks can be enabled in dcd header:
imximage.cfg\mx6ullevk\freescale\board - uboot-imx - i.MX U-Boot
Best regards
igor
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Current situation: Why does the CLkgate bit not set 1 when UBOOT resets the LCDIF block device