imx6sx hangs when setting ENET1_TX_ CLK_DIR in GPR1

[smanni]

Hello,

on a custom design based on imx6sx I have the two FECs providing 50MHz clock to the PHYs on the pads ENET1_TX_CLK and ENET2_TX_CLK.

I have managed to make them work properly in the bootloader (barebox) with the folowing steps:

- set enet_ref rate to 50000000

- set enet2_ref to 50000000

- clear GPR1.bit13 (ENET1_CLK_SEL) and set GPR1.bit17 (ENET1_TX_CLK_DIR)

- clear GPR1.bit14 (ENET2_CLK_SEL) and set GPR1.bit18 (ENET2_TX_CLK_DIR)

Once in the kernel the 50MHz the clock is no longer present on those pins. This is why mach-imx6sx.c clears again GPR1.bit17 and GPR1.bit18 in the function imx6sx_enet_clk_sel():

regmap_update_bits(gpr, IOMUXC_GPR1,         
             IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK, 0);

If I change the function above to set GPR1.bit17 and GPR1.bit18 as follows:

regmap_update_bits(gpr, IOMUXC_GPR1,         
             IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK, IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK);

then the kernel hangs during boot (even the heartbeat LED stops blinking) on the line:

[...]
[    3.314744] imx_thermal 20c8000.anatop:tempmon: Automotive CPU temperature grade - max:125C critical:120C passive:115C
[    3.327342] clk: Disabling unused clocks
 ---- IT HANGS HERE ---

If I try to change both those bits using memtool the result is exactly the same:

# memtool -32 0x20E4004 1
0x020E4004:  0F411005

# memtool -32 0x20E4004=0xf430005
Writing 32-bit value 0xF430005 to address 0x020E4004
###
### IT HANGS HERE

the strange thing is that the problem occurs just when setting GPR1.bit17 (see above) but NOT when setting GPR1.bit18 as below:

# ./memtool -32 0x20E4004=0xf450005
Writing 32-bit value 0xF450005 to address 0x020E4004
[   38.703521] fec 21b4000.ethernet eth1: Link is Up - 100Mbps/Full - flow control rx/tx
###
### NO HANG HERE and eth1 is UP

And in this case and I see a 50MHz clock again on the pin ENET2_TX_CLK, so eth1 is fully working.

Have you ever experienced something like this? The BSP version I'm using is the most recent one: 6.6.3_1.0.0.

Thank you,

Stefano 

[smanni · Accepted solution]

Hello,

I found the solution here:

https://community.nxp.com/t5/i-MX-Processors/IMX6SX-IPG-clock-conflict-IMX-CONSOLE-and-FEC-with-RMII...

Just disabling DTR interrupt in drivers/tty/serial/imx.c fixed the issue.

The reason why I saw the problem only on ENET1 and not on ENET2 is because just the pad ENET1_TX_CLK has the function "DTR_B" (see MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B) but not the pad ENET2_TX_CLK.