imx6q-pcie: phy link never came up, DEBUG_R0: 0x00ea6102, DEBUG_R1: 0x08200000

[wiking]

Observed Phenomenon

Initially, the Wi-Fi module of the device functions normally. However, after approximately two years of use, Wi-Fi-related issues occur. At first, it was suspected that the problem lay with the Wi-Fi module; yet, the same issue persisted even after replacing the Wi-Fi module.

Description

1. The interface of the device's Wi-Fi module is PCIe.
2. The Wi-Fi module uses the PCIe-1 interface of the iMX8 chip (PCIe ports are numbered starting from 1 in the circuit diagram), while PCIe ports in the code are numbered starting from 0. Therefore, it corresponds to "pcie0" in the code.

Logs are as follows:

imx6q-pcie 33800000.pcie: imx pcie probe
OF: PCI: host bridge /pcie@0x33800000 ranges:
OF: PCI:   No bus range found for /pcie@0x33800000, using [bus 00-ff]
OF: PCI:    IO 0x1ff80000..0x1ff8ffff -> 0x00000000
OF: PCI:   MEM 0x18000000..0x1fefffff -> 0x18000000
imx6q-pcie 33800000.pcie: pcie phy pll is locked.
imx6q-pcie 33800000.pcie: phy link never came up
imx6q-pcie 33800000.pcie: DEBUG_R0: 0x00ea6102, DEBUG_R1: 0x08200000

[danielchen]

For the debug info, it is the LTSSM state,  a state machine  defined by the PCI express specification that governs how a PCIe link is established, trained, and maintained.  it transitions through various states during link initialization and operation.

Here are the most common LTSSM states and their hex codes:

Hex Code	LTSSM State	Description
0x00	DETECT_QUIET	No electrical activity detected
0x01	DETECT_ACTIVE	Trying to detect receiver
0x02	POLL_ACTIVE	Sending TS1 ordered sets
0x03	POLL_COMPLIANCE	Compliance pattern testing
0x04	POLL_CONFIG	Sending TS2 ordered sets
0x07	CFG_LINKWD_START	Starting link width configuration
0x08	CFG_LINKWD_ACCEPT	Accepting link width
0x09	CFG_LANENUM_WAIT	Waiting for lane number config
0x0A	CFG_LANENUM_ACCEPT	Accepting lane number config
0x0B	CFG_COMPLETE	Configuration complete
0x11	L0	Link is up and active
0x12	L0s	Low power idle state
0x13	L1	Deeper power saving state
0x17	DISABLED_ENTRY	Entering disabled state
0x18	DISABLED_IDLE	Disabled but idle
0x19	DISABLED	Fully disabled
0x1E	HOT_RESET_ENTRY	Entering hot reset
0x1F	HOT_RESET	In hot reset

when your log shows 

imx6q-pcie 33800000.pcie: DEBUG_R0: 0x00ea6102, DEBUG_R1: 0x08200000

You can extract the LTSSM state from the lowest byte, (0x02  in this case).

0x02 → POLL_ACTIVE → The controller is sending TS1 ordered sets but not receiving a valid response from the endpoint.

This means the PCIe link is stuck in the polling phase, likely due to:

• Endpoint not responding (e.g., Wi-Fi module not powered or reset properly),
• Signal integrity issues,
• Clock or reset timing problems.

[wiking]

SoC: MCIMX8MQ6DVAJZAA
linux-imx:  v4.14.98

dts: fsl-imx8mq-evk.dts