Hi everyone ,
Our custom board is based on imx6q . We need to interface parallel RGB display to our custom board . We modified the below settings in dtsi file
mxcfb1: fb@0 {
compatible = "fsl,mxc_sdc_fb";
disp_dev = "lcd";
interface_pix_fmt = "RGB24";
default_bpp = <24>;
int_clk = <0>;
late_init = <0>;
status = "disabled";
mode_str="LCD"
};
lcd@0 {
compatible = "fsl,lcd";
ipu_id= <0>
disp_id = <0>
default_ifmt="RGB24"
pinctrl_names="default"
pinctrl-0= <&pinctrl_ipu1>
status = "okay"
};
&ldb {
status = "disabled";
lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
primary;
status = "disabled";
display-timings {
native-mode = <&timing0>;
timing0: hsd100pxn1 {
clock-frequency = <51000000>;
hactive = <1024>;
vactive = <600>;
hback-porch = <160>;
hfront-porch = <80>;
vback-porch = <19>;
vfront-porch = <8>;
hsync-len = <60>;
vsync-len = <8>;
};
};
};
lvds-channel@1 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "disabled";
display-timings {
native-mode = <&timing1>;
timing1: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
};
};
then video/fbdev/mxc/mxc_lcdif.c added
static struct fb_videomode lcdif_modedb[] = {
{
/*custom display */
"LCD", 60, 720, 1280,12987, 72, 56, 38, 3, 128, 10, // from custom LCD datasheet
FB_SYNC_CLK_LAT_FALL, //
FB_VMODE_NONINTERLACED,
0,},
};
Problem is there is no pixel clock generated (checked by probing disp0_clk line).
But in cat /sys/kernel/debug/clk/ipu1_pclk0/clk_rate displays 77 MHZ
Is there any other setting missed ? Kindly help me in resolving this issue.
Thanks
Asha
