[Translated by Google]:
Q: At present, the hardware supports LVDS display. Due to the clock limitation,
two LVDSs are combined and implemented by TI DS947 chip (8 channels
of LVDS DATA, 1 channel of CLK). Why is lvds-channel@1 disabled in the
software and the screen still showing normal?
A:
Hi jiu
DS947 chip uses 8 channels for even odd lines, so when channel 1 is disabled
image also can be seen, though with less quality.
Best regards
igor
A:
DS947 chip uses 8 channels for even odd lines, so when channel 1 is disabled
image also can be seen, though with less queslity.
Q: when channel 1 is disabled, channel 1 LVDS_DATA still can be transfered to DS947? Which material should i need to read so that can understand this?
probably one can try with sdk baremetal test (one can find zip on link https://community.nxp.com/thread/432859 ),
then compare ldb settings with linux/android.
Except Reference Manual there is no additional documentation for that mode.
Hi Igor,
So what's the correct config for dts ? split mode?
Hi jiu
yes it is split mode.
Best regards
igor
Hi Igor,
We applied patch for our bsp Patch to support uboot logo keep from uboot to kernel for NXP Linux and Android BSP (HDMI, LCD and L... 0001-Fix-the-split-mode-LVDS-panel-no-TX3-signal-issue.patch L4.1.15_GA1.2.0_uboot_logo_keep_patch_2017-01-06.zip
Once enable LVDS_SPLIT_MODE in mx6sabre_common.h, LCD seems just display half(see below photo), if Disable LVDS_SPLIT_MODE, it seems display OK.
Linux Kernel use [ fsl,data-mapping = "spwg"], it display correct.