imx6 - how to use ddr test tool parameters

[nicehsieh]

Hi everyone,

    I referenced https://community.nxp.com/docs/DOC-105652 and http://www.imx6rex.com/software/how-to-run-ddr3-calibration-on-imx6/

    I used GUI DDR Test Tool V2.52 to test our customer board and it was successful.

    I got some parameters from test tool and it looks like as below

        ...

        Write leveling calibration completed

        MMDC_MPWLDECTRL0 ch0 after write level cal: 0x0012001F

        MMDC_MPWLDECTRL1 ch0 after write level cal: 0x00230011

        MMDC_MPWLDECTRL0 ch1 after write level cal: 0x0017001F

        MMDC_MPWLDECTRL1 ch1 after write level cal: 0x000E001D

        ...

           MMDC registers updated from calibration

           Read DQS Gating calibration

           MPDGCTRL0 PHY0 (0x021b083c) = 0x432C032C

           MPDGCTRL1 PHY0 (0x021b0840) = 0x03240328

           MPDGCTRL0 PHY1 (0x021b483c) = 0x432C033C

           MPDGCTRL1 PHY1 (0x021b4840) = 0x03200268

           Read calibration

           MPRDDLCTL PHY0 (0x021b0848) = 0x3A2E3234

           MPRDDLCTL PHY1 (0x021b4848) = 0x34322A3C

           Write calibration

           MPWRDLCTL PHY0 (0x021b0850) = 0x3C3C4442

           MPWRDLCTL PHY1 (0x021b4850) = 0x44344438

           ...

    But I don't know what's the relationship between those parameters and board/freescale/mx6q_rex/flash_header.S

             #else  /* i.MX6Q */

            dcd_hdr:          .word 0x40a002D2 /* Tag=0xD2, Len=83*8 + 4 + 4, Ver=0x40 */

            write_dcd_cmd:    .word 0x049c02CC /* Tag=0xCC, Len=83*8 + 4, Param=0x04 */

            /* DCD */

            //corrected to 2GB MT41K256M16HA-125:E based on Sabre AI

            MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x798, 0x000C0000)

            MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x758, 0x00000000)

            MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x588, 0x00000030)

            MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x594, 0x00000030)

            MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x56c, 0x00000030)

            MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x578, 0x00000030)

            MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)

Could you give me some advice about this problem ?

[igorpadykov · Accepted solution]

Hi nice

please refer to attached flash_header.S, for example string:

MPDGCTRL0 PHY0 (0x021b083c) = 0x432C032C

corresponds below part of script (with arrow) :

-----------------------------------------------------------------

# MMDC_P0_BASE_ADDR = 0x021b0000

# MMDC_P1_BASE_ADDR = 0x021b4000

# Calibrations

# ZQ

MXC_DCD_ITEM(39, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)

# write leveling

MXC_DCD_ITEM(40, MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F)

MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x810, 0x001F001F)

MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x80c, 0x001F001F)

MXC_DCD_ITEM(43, MMDC_P1_BASE_ADDR + 0x810, 0x001F001F)

# DQS gating, read delay, write delay calibration values

# based on calibration compare of 0x00ffff00

MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x83c, 0x42480248)    <----------------------

...

-----------------------------------------------------------------

Best regards

igor

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[nicehsieh]

Hi igorpadykov,

     Thanks for your reply :smileyhappy: