imx6 CSI bt.1120 issues

[ivankozic]

Hi all,

I have a problem making bt.1120 work on imx6 quad. All the usual problems are solved (IPU driver rewritten; V4L driver rewritten etc). Basically, from i.MX6 point of view everything is set up.

However, it will not capture. I did some investigation and found some weird things in the datasheet (rev 2. CEC):

1. On page 5 (Chapter 1.2 - Features) it is written that i.MX6 supports up to 240 MHz and up to 20 bits for CSI Parallel port.

2. On page 99 (Chapter 4.11.10.3 - Electrical characteristics) it is written that maximum Sensor output (pixel) clock frequency is 180 MHz.

As my clock is 210 MHz, I would really like to know which is correct? I am also using T1.0 silicon, if this is important.

Every help appreciated!

[qiang_li-mpu_se · Accepted solution]

By the way, 240Mhz Parallel Camera port max clock frequency is the correct information for iMX6, 180MHz is for iMX53.

[qiang_li-mpu_se]

The freescale BT1120 CSI reference patch can be found at https://community.freescale.com/message/356584, maybe you can try with lower clock frequency first to idendify the root cause.

[bellzhong]

Hi LiQiang,

I got a custom imx6q sabersd HW platform with ADV7441, the ADV7441 is HDMI ---> CSI encoder, support bt1120 interface. And was able to received BT.1120 progressive data. When tried to received BT.1120 interlaced data, the video was displayed but moving from the top side to the bottom side quickly. Were you able to capture any BT.1120 interlaced video on imx6q sabersd HW platform? If so, any other modification to the code for BT.1120 interlaced data is needed except for setting the clockmode to IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR?

Thank you in advance.

Bell

[qiang_li-mpu_se]

For the screen scroll issue, in kernel file "mxc_v4l2_capture.c", you can adjust the active_top value to fix it.

static video_fmt_t video_fmts[] = {

{   /*! NTSC */

  .v4l2_id = V4L2_STD_NTSC,

  .name = "NTSC",

  .raw_width = 720,  /* SENS_FRM_WIDTH */

  .raw_height = 525,  /* SENS_FRM_HEIGHT */

  .active_width = 720,  /* ACT_FRM_WIDTH */

  .active_height = 480,  /* ACT_FRM_HEIGHT */

  .active_top = 13,

  .active_left = 0,

  },

[ivankozic]

Quick update: It seems (at least for T1.0 silicon) that 180 MHz is the maximum clock speed, as now when I lowered clock frequency to 168 MHz, I am capturing data (still not sure if it's correct data).

If anyone from Freescale is watching - I am still interested in the official information about this, since we are going to purchase T1.2 silicon quite soon.