imx53 Config EIM register as PSRAM, burst access

[wangyx]

   imx53 connect to FPGA via EIM interface. non-multiplexed mode.Config EIM registers as shown below(almost the same to recommend PSRAM's configration of datasheet for imx53RM) that i will burst access FPGA.

// Synchronous Mode 32 bit memory

WR32('EIM_CS0GCR1,'h4003_1487);

WR32('EIM_CS0RCR1,'h04000000);

WR32('EIM_CS0RCR2,'h00000008);

WR32('EIM_CS0WCR1,'h04000000);

    Write(or read) data to(/from) EIM(FPGA), there are always one more times triger access(See attached timing diagram---write1.bmp,write2.bmp,read.bmp), That's the ourtiming diagram.

Expect result:

When burst access, the monitoring timing diagram is PSRAM-like.

ps:when i access to FPGA, the data and address transfer is no problem.

[wangyx]

     Now we can burst access,but the burst lenth cannot change.

However set BL value of CS0GCR1, burst lenth will not change, My project is the same as the FPGA as PSRAM peripherals with imx53 via a EIM.

     Anybody can help me? Give me some advise. What is the situation likely to lead to such this happen ?

ps:Now the write burst is 4 words(our is 32bit), but the lenth of read access is 16 words, why?