iMXRT 1176 not booting from application code (Error: Wire Ack Fault - target connected?)

[HMUser]

Hi,

We have a MaaXBoard RT running with iMXRT 1176 with external Octal SPI flash. We have developed driver and created .cfx file. 

The driver is verified by using Boot utility tool as well as MCUXpresso GUI Flash tool. We are able to successfully Program/Read/Erase extenal flash. So, the driver seems to be working fine.

We are getting an issue during boot-up after loading application file. The MCU boots to flashloader instead of application file.

Below is the console log displayed:

 MCUXpresso IDE RedlinkMulti Driver v11.6 (Jul 12 2022 16:58:24 - crt_emu_cm_redlink build 4)
Found chip XML file in ../flash_cli_freertos_hello_cm7/Debug\MIMXRT1176xxxxx.xml
( 5) Remote configuration complete
Reconnected to existing LinkServer process.
============= SCRIPT: RT1170_connect_M7_wake_M4.scp =============
RT1170 Connect M7 and Wake M4 Script
DpID = 6BA02477
APID = 0x84770001
Setting M4 spin code
Setting M4 clock
Resetting M4 core
Releasing M4
View cores on the DAP AP
DpID = 6BA02477
TAP 0: 6BA02477 Core 0: M7 APID: 84770001 ROM Table: E00FD003*
TAP 0: 6BA02477 Core 1: M4 APID: 24770011 ROM Table: E00FF003
============= END SCRIPT ========================================
Probe Firmware: MCU-LINK r0FF CMSIS-DAP V0.078 (NXP Semiconductors)
Serial Number: XHJPKS3KETS2V
VID:PID: 1FC9:0143
USB Path: \\?\hid#vid_1fc9&pid_0143&mi_00#7&13472939&0&0000#{4d1e55b2-f16f-11cf-88cb-001111000030}
Using memory from core 0 after searching for a good core
debug interface type = CoreSight DP (DAP DP ID 6BA02477) over SWD TAP 0
processor type = Cortex-M7 (CPU ID 00000C27) on DAP AP 0
number of h/w breakpoints = 8
number of flash patches = 0
number of h/w watchpoints = 4
Probe(0): Connected&Reset. DpID: 6BA02477. CpuID: 00000C27. Info: <None>
Debug protocol: SWD. RTCK: Disabled. Vector catch: Disabled.
Content of CoreSight Debug ROM(s):
RBASE E00FD000: CID B105100D PID 000008E88C ROM (type 0x1)
ROM 1 E00FE000: CID B105100D PID 04000BB4C8 ROM (type 0x1)
ROM 2 E00FF000: CID B105100D PID 04000BB4C7 ROM (type 0x1)
ROM 3 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0)
ROM 3 E0001000: CID B105E00D PID 04000BB002 Gen DWT (type 0x0)
ROM 3 E0002000: CID B105E00D PID 04000BB00E Gen (type 0x0)
ROM 3 E0000000: CID B105E00D PID 04000BB001 Gen ITM (type 0x0)
ROM 2 E0041000: CID B105900D PID 04001BB975 CSt ARM ETMv4.0 type 0x13 Trace Source - Core
ROM 2 E0042000: CID B105900D PID 04004BB906 CSt type 0x14 Debug Control - Trigger, e.g. ECT
ROM 1 E0043000: CID B105900D PID 04001BB908 CSt CSTF type 0x12 Trace Link - Trace funnel/router
NXP: MIMXRT1176xxxxx
DAP stride is 1024 bytes (256 words)
Inspected v.2 External Flash Device on SPI MaaxBoard_RT_OPI.cfx
Image 'iMXRT1170_SFDP_FlexSPI1_OPI Oct 17 2022 10:32:00'
Opening flash driver MaaxBoard_RT_OPI.cfx
Sending VECTRESET to run flash driver
Flash variant 'iMXRT1170_SFDP_FlexSPI1_OPI Oct 17 2022 10:32:00' detected (32MB = 256*128K at 0x30000000)
Closing flash driver MaaxBoard_RT_OPI.cfx
Connected: was_reset=true. was_stopped=false
Awaiting telnet connection to port 3330 ...
GDB nonstop mode enabled
FreeRTOS stack backtrace is disabled in Non-stop mode (use All-stop)
Opening flash driver MaaxBoard_RT_OPI.cfx (already resident)
Sending VECTRESET to run flash driver
Flash variant 'iMXRT1170_SFDP_FlexSPI1_OPI Oct 17 2022 10:32:00' detected (32MB = 256*128K at 0x30000000)
Writing 59900 bytes to address 0x30000000 in Flash
Sectors written: 0, unchanged: 1, total: 1
Erased/Wrote sector 0-0 with 59900 bytes in 28msec
Closing flash driver MaaxBoard_RT_OPI.cfx
Flash Write Done
Flash Program Summary: 59900 bytes in 0.03 seconds (2089.15 KB/sec)
============= SCRIPT: RT1170_reset.scp =============
SYSTEM Reset
DpID = 6BA02477
APID = 0x84770001
Tokenizer error - at character '\x9'
Setting M4 spin code
Setting M4 clock
Resetting M4 core
Releasing M4
View cores on the DAP AP
DpID = 6BA02477
TAP 0: 6BA02477 Core 0: M7 APID: 84770001 ROM Table: E00FD003*
TAP 0: 6BA02477 Core 1: M4 APID: 24770011 ROM Table: E00FF003
R15 = 0x00223104
Error: Wire Ack Fault - target connected?
Error: Wire Ack Fault - target connected?
Error: Wire Ack Fault - target connected?
Error: Wire Ack Fault - target connected?
Error: Wire Ack Fault - target connected?
Vector table SP/PC is the reset context.
PC = 0x00000200
SP = 0x00000200
XPSR = 0x01000000
VTOR = 0x30002000
Error: Wire Ack Fault - target connected?
Set DEMCR = 0x010007F1
Error: Wire Ack Fault - target connected?
============= END SCRIPT ===========================
state - running or following reset request - re-read of state failed - rc Nn(05). Wire ACK Fault in DAP access
state - running or following reset request - re-read of state failed - rc Nn(05). Wire ACK Fault in DAP access
state - running or following reset request - re-read of state failed - rc Nn(05). Wire ACK Fault in DAP access
following reset read of core registers failed - Ep(08). Cannot access core regs when target running.
Target error from Commit Flash write: Ep(08). Cannot access core regs when target running.
GDB stub (C:\nxp\MCUXpressoIDE_11.6.0_8187\ide\plugins\com.nxp.mcuxpresso.tools.bin.win32_11.6.0.202207121507\binaries\crt_emu_cm_redlink) terminating - GDB protocol problem: Pipe has been closed by GDB.
state - running or following reset request - re-read of state failed - rc Nn(05). Wire ACK Fault in DAP access

iMXRT1170

[jay_heng]

Your created flash algo file is MaaxBoard_RT_OPI.cfx? does it enable OPI mode for flash during downloading? if so, there may be ROM boot issue after core softreset. as BootROM always try to read boot header from flash via SPI mode then switch flash to OPI mode, but you have enabled OPI in flashloader, BootROM cannot read boot header properly.

You can refer to below blog (it is in chinese) to enable BootROM SW reset function to fix this issue.

https://www.cnblogs.com/henjay724/p/15085155.html

const flexspi_nor_config_t flash_config = {
    .flashStateCtx = 0x07008200u,  //!< [0x1d4-0x1d7] //
};

[HMUser]

Hi @jay_heng,

Thanks a lot for your reply.

The blog is very much informative. Yes, the driver does enable OPI mode during flash image download.

As per the blog, there are 3 ways to reset external flash and also it is necessary to reset flash along with soft reset.

One way to reset is using hardware pin RESET# from flash.

We have developed Octal flash driver on the basis of iMXRT117x_FlexSPI_SFDP project.

The flash driver project from NXP (iMXRT117x_FlexSPI_SFDP) uses GPIO_AD_03 as RESET#, but we need to use GPIO_SD_B2_11 to reset flash.

Below code section is from iMXRT117x_FlexSPI_SFDP, which resets flash using RESET# pin.

// ****************
// Reset external flash via GPIO

// The problem with the external flash reset is that the actual pin
// that is being used is board-specific: EVK boards use GPIO_AD_03,
// but custom boards can use anything!
// Please update this section accordingly
// GPIO_AD_03 -> routed to GPIO port 9, pin 2
#define PIN_MASK (1 << 2)

// Enable clock to IOMUX (LPCG49)
uint32_t lpcg = MEM_ReadU32(0x40cc6620);
if (!(lpcg & 1))
{
// CCM->LPCG49 = EN (IOMUX)
MEM_WriteU32(0x40cc6620, (lpcg | 1));
__asm volatile ("dsb 0xF":::"memory");
__asm volatile ("isb 0xF":::"memory");
}

// Enable clock to GPIO_9 (LPCG51)
lpcg = MEM_ReadU32(0x40cc6660);
if (!(lpcg & 1))
{
// CCM->LPCG51 = EN (GPIO_9)
MEM_WriteU32(0x40cc6660, (lpcg | 1));
__asm volatile ("dsb 0xF":::"memory");
__asm volatile ("isb 0xF":::"memory");
}

// Disable interrupt GPIO9->IMR &= ~(1 << pin)
uint32_t imr = MEM_ReadU32(0x40c64014);
MEM_WriteU32(0x40c64014, imr & ~PIN_MASK);
// Set DIR (output) GPIO9->GDIR |= (1 << pin);
uint32_t dir = MEM_ReadU32(0x40c64004);
MEM_WriteU32(0x40c64004, dir | PIN_MASK);
// Drive high GPIO9->DR_SET = (1 << pin);
MEM_WriteU32(0x40c64084, PIN_MASK);

// Route to GPIO IOMUX->SW_MUX_CTL_PAD_GPIO_AD_03 = 0xA
MEM_WriteU32(0x400e8118, 0xa);

MEM_WriteU32(0x400e835cu, 0x12);

// Toggle GPIO9->DR_TOGGLE = (1 << pin);
MEM_WriteU32(0x40c6408c, PIN_MASK);
// Delay some time to reset external flash
for (uint32_t i = 0; i < 3000000; i++)
__asm volatile ("nop");
// Toggle GPIO9->DR_TOGGLE = (1 << pin);
MEM_WriteU32(0x40c6408c, PIN_MASK);
for (uint32_t i = 0; i < 3000000; i++)
__asm volatile ("nop");
// ****************

Could you please guide me on how to do above operation from gpio pin GPIO_SD_B2_11?

[jay_heng]

GPIO_AD_03 -> GPIO9[2]

GPIO_SD_B2_11 -> GPIO10[20]

You can refer to below example for GPIO operation:

\SDK_2.12.0_MIMXRT1170-EVK\boards\evkmimxrt1170\driver_examples\gpio\led_output

[HMUser]

Hi @jay_heng 

Thanks for the reply.

Sorry, for the late response.

I was able to reset the external flash using HW #RESET pin. But, still no luck with the issue. I'm facing same issue.

I was going through the blog https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/RT1170-Octal-flash-enablement/ta-p/1498369.  And found that LUT under FDCB is key to resolve the issue.

Can you please help us with more information on what must be included in const flexspi_nor_config_t octalflashconfig?

Currently, I'm using below configuration -

const flexspi_nor_config_t octalflash_config = {
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc =kFlexSPIReadSampleClk_ExternalInputFromDqsPad,
.csHoldTime = 3,
.csSetupTime = 3,
.deviceModeCfgEnable = 1,
.deviceModeType = kDeviceConfigCmdType_Spi2Xpi,
.waitTimeCfgCommands = 1,
.deviceModeSeq =
{
.seqNum = 1,
.seqId = 6, /* See Lookup table for more details */
.reserved = 0,
},
.deviceModeArg = 0xE7, /* Enable OPI DDR mode */
.controllerMiscOption =
(1u << kFlexSpiMiscOffset_DdrModeEnable) |// (1u << kFlexSpiMiscOffset_WordAddressableEnable) |
(1u << kFlexSpiMiscOffset_SafeConfigFreqEnable),// | (1u << kFlexSpiMiscOffset_DiffClkEnable,// | (1u << kFlexSpiMiscOffset_ParallelEnable),
.deviceType = kFlexSpiDeviceType_SerialNOR,
.sflashPadType = kSerialFlash_8Pads,
.serialClkFreq = kFlexSpiSerialClk_166MHz,
.sflashA1Size = 32ul * 1024u * 1024u,
.dataValidTime ={16u, 16u},
.busyOffset = 0u,
.busyBitPolarity = 0u,
.lookupTable =
{
/* Read -DDR */
// FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_8PAD, 0xFD, RADDR_DDR, FLEXSPI_8PAD, 0x20),
// FLEXSPI_LUT_SEQ(DUMMY_DDR, FLEXSPI_8PAD, 0x06, READ_DDR, FLEXSPI_8PAD, 0x04)
[0 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_8PAD, 0xFD, RADDR_DDR, FLEXSPI_8PAD, 0x20),
[0 + 1] = FLEXSPI_LUT_SEQ(DUMMY_DDR, FLEXSPI_8PAD, 0x25, READ_DDR, FLEXSPI_8PAD, 0x04),

// /* Read Status SPI *///
[4*1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04),
//
// /* Read Status OPI */
[4*2 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_8PAD, 0x05, READ_DDR, FLEXSPI_8PAD, 0x04),
//
// /* Write enable SPI *///06h
[4*3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0),
// /* Write enable OPI *///06h
[4*4 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_8PAD, 0x06, STOP, FLEXSPI_1PAD, 0),

/* Erase sector */ //21H
[4*5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_8PAD, 0x21, RADDR_DDR, FLEXSPI_8PAD, 0x20),
//
// //Write Volatile configuration to enable DDR
[4*6 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x81, CMD_SDR, FLEXSPI_1PAD, 0x00),
[4*6 + 1] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x00, CMD_SDR, FLEXSPI_1PAD, 0x00),
[4*6 + 2] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x1, STOP, FLEXSPI_1PAD, 0),
//
/*block erase*/ //DC
[4*8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_8PAD, 0xDC, RADDR_DDR, FLEXSPI_8PAD, 0x20),

/*page program*/ //12H
[4*9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_8PAD, 0x12, RADDR_DDR, FLEXSPI_8PAD, 0x20),
[4*9 + 1] = FLEXSPI_LUT_SEQ(WRITE_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0),

/* Chip Erase (CE) Sequence *///60
[4*11 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_8PAD, 0x60, STOP, FLEXSPI_1PAD, 0),

},
},
.pageSize = 256u,
.sectorSize = 128u * 1024u,
.blockSize = 128u * 1024u,
.isUniformBlockSize = true,
.serialNorType = 0x02,
.flashStateCtx = 0x07008200u,
};

Could you please the verify the above configuration for octal flash IS25WX256?

[jay_heng]

Please refer to attached FDCB we have ever used for Micron MT35XU512.

From cmd set, IS25WX256 is same as MT35XU512

Besides i have created one project to test all kinds of Flash, IS25WX256 is covered.

https://github.com/JayHeng/RT-MFB/tree/main/boards/mimxrt/mfb_fw/src

[HMUser]

Thanks a lot for sharing the project.

I'm able to successfully execute the application code(LED blinky), which is stored in external octal flash using the shared mfb project to jump to the application address. The mfb project was selected to "Link application to RAM" configuration in the above process.

What we are trying to do is, to run the external application code without the need of secondary bootloader (mfb project). Can you please help us in this direction?
  

If we try to debug the application code with the updated FDCB and unchecking the "Link application to RAM", we are still getting same error logs.

Below image is for your reference.

[HMUser]

Hi @jay_heng,

Could you please help us to resolve the issue?

We have further analyzed the logs of RT1170_reset.scp, we found that the "Error: Wire Ack Fault - target connected?" comes soon after the operation "b% = Peek32 This d%", i.e., at the address 0x3000200 where vector table is located.

We have verified the application hex file. The application file has valid vector table at address 0x300200. But the script is not able to read the contents of vector table.