Hello all to whom it may concern,
I am currently designing the USB3 connection application based on iMX8QM host processor and have got substantially good results of phy characteristics
except tx eye opening, which is slightly cross the limit..
As far as I understand, the PCIe transceiver has some register to tune the voltage swing for adopting some application purpose (such as eye opening), and USB3 PIPE I/F have similar PHY structure so that it may be possible
to access and set the appropriate value for satisfying USB3 requirement.
Reviewing iMX8 Reference manual, I could not find any related results for the setup register especially TxMargin[2..0],TxSwing.
I am also trying to improve the artwork of USB differencial pair much more precisely, however does someone who knows about that more details of register setting for USB3?
Or is there any solution to improve the voltage swing for USB3 signal lane?
I am looking forward to see your comments, thank you very much in advance.
