iMX8MP LPDDR4 Signal Integrity Simulation

[massimomantovan]

Hi

I would like to know if it is possible to have the simulation settings that were used in the EVK iMX8MP?
Because in the Hardaware manual there is not much reference to this.
particularly in the board I am simulating I get good eye diagrams in the write cycle, while in the read cycle the diagrams are definitely worse in terms of eye distortion. I have tried changing the various driver and receiver settings but without getting significant results.
So I would like to start with the EVK settings.

And if you have any other suggestions on other settings or anything else please tell me.

Thanks

[Chavira]

Hi @massimomantovan!

Are you using our DDR Tool?

You can see our default setting in the DDR Tool but if you are trying to train your custom design you should use our DDR tool to get the proper configuration according to your hardware.

Our DDR Tool can be used installing Config Tools for i.MX Applications Processors 

Best Regards!

Chavira

[massimomantovan]

Hi @Chavira 

Thank you for your reply.

I haven't used your DDR tool yet because my project is not finished yet, it's 90%. but before we go ahead and build the PCB we would like to do a round of simulations to validate the integrity of the LPDDR4 memory bus signals.

I just wanted to know the model selector configuration of the iMX8MP EVK to have a starting point for the simulation.
But probably just running the DDR tool connected to the EVK is enough to get the model selector configuration.

Regarding Signal Integrity simulation, besides the Hardware manual of the iMX8MP (IMX8MPHDG.pdf) is there any other more comprehensive document?

Thank you

Massimo 

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