iMX8MP DRAM Traininig Fail

[denizkcts]

Hello,

We have designed an iMX8Mp custom board. DRAM part number is MT53E512M32D1ZW-046WT:B. 

In layout design we have followed the HDG. Package delays and trace delays are considered.

We just couldnt find the DRAMs package delay info. Maybe this could causes the issue.

And other issue in my mind is delay between channels. There is no restriction mentioned in HDG about this. Delay difference between clocks of A and B channels is about 30-40 ps.

Please help someone 

With following configuration:

we get following  result:

[denizkcts]

Hi @pengyong_zhang 

Thanks for your reply.

We had already ran the test with this tools previous version and with this configuration and result was same.

After your reply, we ve tried again with the latest version and same result.

Please see the log we have after the tests.

Ps. I forgot to mention in first post that we have ran boundary scan test and all channels have passed the tests. I mean PCB seems OK, but boundary scan test is kinda static. We have ran at maximum TCK frequency but still the speed may not enough.

Regards

[pengyong_zhang]

Hi @denizkcts 

Please use our latest Config Tool version run the DDR related tests. And use the below configuration.

B.R