Hi,
Our new project on basis iMX8m, should include low power/deep sleeping mode with desired power consumption less than 10 mW
For its implementation we intend to provide followings steps:
1. To set PIMIC in Sleeping Mode (deasserted PMIC_ON_REQ signal from iMX8M to PWRON pin of PIMIC), so that only the power for the SNVS domain remains on for iMX8M. ( according to data sheet this mode called SNVS Mode, see paragraph 3.1.6)
2. To set DDR Memories in the Self Refresh Mode.
3. iMX8M will be wake Up from low power/deep sleeping mode through ONOF signal, and after this it will assert PMIC_ON_REQ signal for PIMIC
Please confirm that iMX8M support those steps, and after wake-up from SNVS Mode it will be able to continue programs from the same point without the system reset.
Thank You,
Boris
Hi Igor,
Thank you for Your fast answer!
From your answer I still did not understand, can I exit from SNVS/RTC mode and continue programs from the same point that before entered in this mode.
I would like to note that for data retain the external LPDDR4 memory i mean to enter in the self-refresh mode, but necessary power supply for the proper SELF REFRESH operation, will be supplied on the external LPDDR4 memory only, and no on the DRAM controller (VDD_DRAM power domain) and NVCC_DRAM power domain of iMX8M.
Thank You,
Boris
Hi Igor,
Thank you for cooperation!
Best Regards,
Boris
Hi Boris
yes ON/OFF pin can wake up the system from SNVS mode.
Regarding DDR Memories, according to sect.3.1.6 Power modes i.MX8MDQ Datasheet :
SNVS Mode: This mode is also called RTC mode. Only the power for the SNVS domain remains
on to keep RTC and SNVS logic alive.
https://www.nxp.com/docs/en/data-sheet/IMX8MDQLQCEC.pdf
for deep sleep mode use cases one can look on AN12118 i.MX8M Quad Power Consumption Measurement
https://www.nxp.com/docs/en/nxp/application-notes/AN12118.pdf
Best regards
igor
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Hi Igor,
Thank you for Your fast answer!
From your answer I still did not understand, can I exit from SNVS/RTC mode and continue programs from the same point that before entered in this mode.
I would like to note that for data retain the external LPDDR4 memory i mean to enter in the self-refresh mode, but necessary power supply for the proper SELF REFRESH operation, will be supplied on the external LPDDR4 memory only, and no on the DRAM controller (VDD_DRAM power domain) and NVCC_DRAM power domain of iMX8M.
Thank You,
Boris