iMX7D : How to determine eLCDIF Read timing ?

[koichisakagami]

Dear community,
We have been developing our product with iMX7D.

I am planning to use LCDIF MPU mode.
I check an eLCDIF read timing with Figure 13-14 "Read timing interface in 6800 and 8080 protocols"
in the Reference Manual IMX7DRM (page 3639).

I know that LCD Interface Timing Register (LCDIFx_TIMING) is used for setting to CMD setup/hold and DATA setup/hold.But I can not find a register constituting the timing except LCDIFx_TIMING register.

[Question]
So,
    Could you tell me how to determine the timing  as follows.
        1.timing width (W1 + W3)
        2.required timing for TDSR and TDHR
        3.LCD_RD_E low pulse width , LCD_RD_E high pulse width

Best Regards,
       Koichi Sakagami

[art]

1. W1, W2 and W3 are the internal delays, caused by data transfer delay on the processor's internal bus. These delays are variable by their nature, but relatively small versus the period of the DISPLAY_CLK clock that defines the LCDIF timings in the MPU mode.

2. TDSR and TDHR are the Data Setup and Data Hold times, as defined in the LCDIF_TIMING register, correspondingly.

3. The Data Setup and Data Hold times, together with small Wx delays, define the parameters of the LCD_RD_E pulse.

Have a great day,
Artur

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------