iMX7 MIPI DSI not entering stop state

[steveschefter]

We are attempting to use the MIPI DSI interface in u-boot on a custom board which uses the iMX7S5EVM08SC. The interface works in Linux so we know there are no hardware issues. With debugging added to writes to the MIPI_DSI registers in both u-boot and Linux, all are being set the same and yet in u-boot, we are unable to send a command to the display.

I tried following the Command Initialization steps, number 7 in Table 13-15.

First question: When it says for step 2, "SFR_Write(Display Controller_registers, S-i80, IF_888" what register setting is it referring to? Register MIPI_DSI_CONFIG has a setting for 888, but that register is initialized in step 6.  The MIPI_DSI_RGB_STATUS has a bit for S-i80 versus RGB, but that register is read-only.

We are not able to get past step 10 because the clock and data lanes never enter stop state. The register MIPI_DSI_STATUS remains at 0x001002f0 no matter how long we wait. The description for step 10 indicates that it forces stop state by default after reset or power on, but that's not happening.

Second/main question: What can prevent it from entering stop state?

This led me to wonder if there might be a clocking issue with either MIPI_DSI or with its DPHY. However, the setup looks correct and is consistent with what I see in Linux.

MIPI_DSI_CLK_ROOT = 10000000
MIPI_DPHY_REF_CLK_ROOT = 10000000
So both clocks are enabled and their roots are OSC_24M

CCM_CCGR101 = 3
CCM_CCGR102 = 3
So the domain clocks for MIPI_DSI and MIPI_PHY clocks are needed all the time.

Third question: Are there any other clocks involved which might prevent proper operation of MIPI_DSI?

Here are the registers that I've written and the lack of stop state that I observe:

wrote 02017700 to MIPI_DSI_CONFIG
wrote 00001000 to MIPI_DSI_CLKCTRL
wrote 050002d0 to MIPI_DSI_MDRESOL
wrote 0d0177f7 to MIPI_DSI_CONFIG
wrote 00806320 to MIPI_DSI_PLLCTRL
wrote 0 to MIPI_DSI_ESCMODE
MIPI_DSI_STATUS stuck at 001002f0

The status register does not have the STOPSTATECLK or STOPSTATEDAT bits set.  In Linux, this register is 0x001001c3 so those bits are set.

[steveschefter]

NXP created a support ticket regarding this, but the support portal is broken at the moment (looks like a Salesforce issue).  So I'm replying in here in hopes that the support folks will see it as I have no other way to follow up.

On 2023-03-22 5:02 a.m., NXP Tech Support wrote:

Please make sure the connection of mipi-dsi with external display are made properly as shown in the image.

There wasn't an attachment with an image in the e-mail that the portal sent.  However, I can confirm that the display connections are correct since the display works under Linux.  We are just trying to get it to work under u-boot as well.

Command mode uses RGB interface and S-i80 interface. Mode can change via SFRs.

Please make sure mipi-dsi needs high frequency clock generated by PLL.

I have:

CCM_CCGR101 = 3
CCM_CCGR102 = 3

So the MIPI_DSI_CLOCK_ROOT and MIPI_PHY_CLOCK_ROOT is set to "Domain clocks needed all the time".

CCM_TARGET_ROOT71 = 10000000

CCM_TARGET_ROOT73 = 10000000

So the root clock is enabled and the mux setting is OSC_24M.

I believe I therefore have all the clocks needed for both MIPI DSI and its DPHY.  But if there are more clocks involved, please let me know.

One can use Buffer, in MIPI DSI standard specification, DSI Master sends image stream in burst mode. The image stream transmits in high-speed and bit-clock frequency. This mode allows the device to stay in stop state longer to reduce power consumption.

For this mode, MIPI DSI Master has a line buffer to store one complete line and send it faster at the next line time.

We are attempting to to send a command to the display to initialize it.  So we are not yet to the point of sending an image stream.

If one is using command mode Please make sure of the below-given thing.

Command mode starting sequence:

1. Set S-i80 I/F in Display Controller (RGB888), also set Command mode at MIPI DSI Master

I see that is the first step in Command Initialization in table 13-15 in the iMX7S RM.  But the meaning of that step is unclear.

I see 888 settings in the DSI_CONFIG, but that is set in step 6.  Also, the MIPI_DSI_RGB_STATUS register has a way to see RGB video versus S-i80, but that is a read-only register according to the RM.

So what does "Set S-i80 I/F in Display Controller (RGB888), also set Command mode at MIPI DSI Master" mean in terms of register settings?

2. Configure all parameters for displaying an image.

That is done.  We are setting the parameters the same in u-boot as we are in Linux.  Specifically:
00000000 --> MIPI_DSI_CLKCTRL
00806320 --> MIPI_DSI_PLLCTRL
00008100 --> MIPI_DSI_PLLTMR
1138000a --> MIPI_DSI_CLKCTRL
050002d0 --> MIPI_DSI_MDRESOL
22017727 --> MIPI_DSI_CONFIG
f00e0008 --> MIPI_DSI_MVPORCH
000c0012 --> MIPI_DSI_MHPORCH
01800008 --> MIPI_DSI_MSYNC
0000060a --> MIPI_DSI_PHYTIMING
07230c07 --> MIPI_DSI_PHYTIMING1
00080c0a --> MIPI_DSI_PHYTIMING2
000f000f --> MIPI_DSI_TIMEOUT
0 --> MIPI_DSI_FIFOCTRL
delay 300us
1F --> MIPI_DSI_FIFOCTRL

3. Set the command at MIPI DSI registers using MIPI DCS.

We do that, but the command does not get shifted out of the FIFO:
00000080 --> MIPI_DSI_ESCMODE
20040000 --> MIPI_DSI_INTSRC
dffbffff --> MIPI_DSI_INTMSK
before writing data MIPI_DSI_STATUS = 001002f0
                    MIPI_DSI_FIFOCTRL = 0155551f
23 --> DSIM_PKTHDR

In u-boot after the write,  MIPI_DSI_FIFOCTRL = 0115551f and it remains that way forever.  So the packet is stuck in the FIFO.

Given the clock setup indicated above, what would prevent it from shifting the command out of the FIFO?

4. S-i80 I/F is just used to transmit image data. The users have to read the display peripheral status and write commands through MIPI DSI registers.

MIPI_DSI_STATUS -> This register reads and checks internal and interface status.

as per the field description, bit-8 STOPSTATECLK should be 1 to stop state in clock lane.

              bit3:0 STOPSTATEDAT[3:0] should be 0010 as mentioned in RM.

We are using two lanes, so I think STOPSTATEDAT[3:0] should be 0011.

But that's the problem I described in my initial report -- it isn't going to stop state.

I put a print in Linux and in u-boot for every MIPI DSI register access and observe the same writes (copied above).  For Linux, I see the expected stop state for both clock and data (MIPI_DSI_STATUS = 001001c3).  But not for u-boot (MIPI_DSI_STATUS 001002f0).  Thus my question: What can prevent it from entering stop state?

In MIPI_DSI_RGB_STATUS -> RGBSTATE[12:0] should be 0x0002 in case of STOP, please check it too.

When it is stuck, MIPI_DSI_RGB_STATUS 0x00000001 so it is in IDLE rather than STOP state.  Again, it leads to my question.  What can prevent it from entering stop state?

Please kindly share the document, you are following.

I am following "i.MX 7Solo Applications Processor Reference Manual"  The same information is in the 7Dual RM.

Regards,
    Steve

[Sanket_Parekh]

Hello @steveschefter ,

I hope you are doing well.

Please make sure the connection of mipi-dsi with external display are made properly as shown in the image.
Command mode uses RGB interface and S-i80 interface. Mode can change via SFRs.

Please make sure mipi-dsi needs high frequency clock generated by PLL.
One can use Buffer, in MIPI DSI standard specification, DSI Master sends image stream in burst mode. The image stream transmits in high-speed and bit-clock frequency. This mode allows the device to stay in stop state longer to reduce power consumption.
For this mode, MIPI DSI Master has a line buffer to store one complete line and send it faster at the next line time.

If one is using command mode Please make sure of the below-given thing.
Command mode starting sequence:
1. Set S-i80 I/F in Display Controller (RGB888), also set Command mode at MIPI DSI Master
2. Configure all parameters for displaying an image.
3. Set the command at MIPI DSI registers using MIPI DCS.
4. S-i80 I/F is just used to transmit image data. The users have to read the display peripheral status and write commands through MIPI DSI registers.

MIPI_DSI_STATUS -> This register reads and checks internal and interface status.
as per the field description, bit-8 STOPSTATECLK should be 1 to stop state in clock lane.
bit3:0 STOPSTATEDAT[3:0] should be 0010 as mentioned in RM.

In MIPI_DSI_RGB_STATUS -> RGBSTATE[12:0] should be 0x0002 in case of STOP, please check it too.

Please kindly share the document, you are following.

Thanks & Regards,

Sanket Parekh

[steveschefter]

Hi @Sanket_Parekh .  I received the response you posted here previously in an e-mail.  See my post just before yours.  It answers your questions.

    Steve

[Sanket_Parekh]

hello @steveschefter 

I hope you are doing well.

Please kindly share the external display that you are using.
->Please check that the display is supported by u-boot via reference to the u-boot source code.

Thanks & Regards.

Sanket Parekh

[steveschefter]

Hi @Sanket_Parekh

The display is based on the ILI9881.

There is no DSI display on the iMX7 supported in u-boot.  Adding that is what this is about.

Note that my questions are about getting the iMX7 to shift bits out of the FIFO in the DSI interface through the MIPI DPHY.  I am not yet dealing with whether the commands to be shifted are the right ones for this particular display.  DSI is not entering stop state as the RM says it should and the command bytes are stuck in the FIFO.  My questions are about why that's happening.

    Steve

[Sanket_Parekh]

Hello @steveschefter ,

I hope you are doing well.

One can refer to the below file that explains the configuration to be set for the display that one is using.
Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml
Please check the configuration for the same.

To shift bits out of the FIFO in the DSI interface through the MIPI DPHY Can you please share the command sequence that you followed to debug further?
Kindly share the documents that you follow as well as the logs when you give the commands to do the same.

Thanks & Regards,

Sanket Parekh

[steveschefter]

Hi @Sanket_Parekh

> One can refer to the below file that explains the configuration to be set for the display that one is using.
> Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml
> Please check the configuration for the same.

That provides information on how to set up the device tree in Linux.  As I indicated above, the panel is already working in Linux.  We are trying to add support in u-boot.

Also, I'd like to reiterate that the issue is not (yet) about the specifics of this panel.  Nothing is being sent to the panel by MIPI DSI, so it is not the case the the wrong initialization sequence is being sent out the MIPI DSI lines for this panel.  My questions are about how to get MIPI DSI to start sending, not about the details of how to support this particular panel once MIPI DSI starts doing that.

> To shift bits out of the FIFO in the DSI interface through the MIPI DPHY Can you please share the
> command sequence that you followed to debug further?

Please see my second posts in this thread.  I provided the sequence of MIPI DSI register reads and writes that we are performing, as well as the clock settings.  See the section starting with "00000000 --> MIPI_DSI_CLKCTRL"

> Kindly share the documents that you follow.

As I indicated earlier when you asked that, I am following "i.MX 7Solo Applications Processor Reference Manual".

Regards,
    Steve