iMX7 LPDDR3 Length Matching

[pushpanathan]

Hi,

We are planing to use IMX7 processor with LPDDR3.

In the LPDDR3 Length Match Guideline its given as

"Match the signals of each byte group ± 55 mils to the strobe. Limit minimum DQS length to Clock (min) – 200 mils.If the DQS strobe is more than 200 mils shorter than Clock (min), consider manually adjusting each field of register

DDR_PHY_LVL_CON0. Increment +1 for each 100 mils that the DQS trace is shorter than Clock (min)."

1. What is the maximum "DQS Strobe" signal length that we need to maintain? In guideline they mentioned "DQS Strobe" minimum value.(i.e..Limit minimum DQS length to Clock (min) – 200 mils) but they did't talked about maximum length value. Can any one tell what is the maximum value that we need to maintain.
2. In guideline they mentioned if "DQS strobe is more than 200 mils shorter than Clock (min), consider manually adjusting each field of register DDR_PHY_LVL_CON0. Increment +1 for each 100 mils that the DQS trace is shorter than Clock (min).". If we followed above rule anyone faced any issue? pls confirm.
3. In the Reference manual did not give much details about the Register DDR_PHY_LVL_CON0. They have given as Write Level Slave DLL Code Value for Data_Slice 0 ,1,2,3.    Can Any one share the details of these register and its usage

Thanks & Regards,
Pushpanathan

[igorpadykov]

Hi Pushpanathan

according to Table 19. DDR trace routing guidelines Hardware Development Guide

for i.MX7Dual and 7Solo Applications Processors
http://www.nxp.com/files/32bit/doc/user_guide/IMX7DSHDG.pdf

DQS strobe should have maximum length of Clock -10 mils

It is based upon allocating various margins of error for each of the areas that could affect
DDR timing, and still provide a safety margin to ensure that DDR operations fall within the requirements of the
JEDEC standards. Margins of error include areas such as: Internal silicon design, variances through the pads/
balls, PCB design variances, variences for the LPDDR3 device.

Best regards
igor
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