iMX7 Dual, halt CPU by JTAG

[tamotsu]

The title is the same as the question posted by cyuk on 09-07-2017, but the phenomenon in my case is different.

A parallel NOR flash is used as the boot element. I am debugging IVT using Segger's J-Link + J-FLash.

At first I was able to connect, but as I poceeded to change the IVT, the message "Failed to temporarily halting CPU for reading CP15 registers"  appeared and I was unable to connect.

Is there a way to improve it ?

Best regards.

[tamotsu · Accepted solution]

Similar questions have been asked by manufacturers other than NXP.

In conclusion, I found that this error occurs when the voltage somewhere in the circuit is not normal. 

I resolved the error by checking all voltagfes on the circuit.