iMX7 DDR package timing offsets

[joelgroves]

Hi,

I am using the 19x19mm iMX7 package (specifically part MCIMX7D5EVM10SC). We are heading to layout phase and I need to know the DDR pin to die lengths for trace length matching. 

If it isn't already clear what I'm asking, I'll re-iterate for clarity... If the internal distance from BGA ball to die is different and not taken into account already by internal fixed delays within the SoC, then trace matching must take into account the ball to die lengths as this forms the total path from memory to controller.

Can anyone educate me here please?

Thanks,

Joel

[gusarambula]

Hello Joel,

The inner die lengths for the DDR interface are not publicly available. If you follow the guidelines for DDR routing in table section 3.4 of the i.MX7 HW Development Guide (link below) your design should work correctly. These are simple guidelines that ensure that your design can be correctly calibrated, as the memory controller is very flexible.

https://www.nxp.com/docs/en/user-guide/IMX7DSHDG.pdf

I hope this information helps!

Regards,