iMX6DQ LPDDR2 Initialization Issue

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iMX6DQ LPDDR2 Initialization Issue

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rp123
Contributor II

I am trying to configure LPDDR2 on a custom iMX6DQ board and am having issues. Every time I perform a read I get back something different and when I write I do not see it being stored.

 

(gdb) monitor mdw 0x80000000 8

0x80000000: 10e63e50 d13f3450 f43ec9c5 728b8190 080050cf 65507050 dc391598 0010f206

(gdb) monitor mww 0x80000000 0xffffffff

(gdb) monitor mdw 0x80000000 8

0x80000000: 100000ff 908b0050 08ffffc5 723f3490 ffb4c95e d1108184 d0395098 00507006

(gdb) monitor mdw 0x80000000 8

0x80000000: 10e660ff 10e66050 10e660c5 723f8190 08ffc95e d18b3484 ff00ff98 0050f206

(gdb) monitor mdw 0x80000000 8

0x80000000: 08e66050 72e62090 ffe6c9c5 d18b8150 d000ffff 003f3406 dcff1598 6510f284

(gdb) monitor mdw 0x80000000 8

0x80000000: 10e66050 d1e66050 ffe6ffc5 723f3490 08ffc9ff 658b8150 dc005098 00507006

(gdb) monitor mdw 0x80000000 8

0x80000000: ffe66050 d1e66050 080060c5 728b8190 dcffc9ff 653f3450 d0b4ff98 0010f206

 

The board is a single channel configuration using Micron’s DDR2 MT42L256M32D2LG-18 WT:A

I set the memory mapping mode to Dual channel (2x 32-bit), Fixed mapping (LPDDR2) (which starts from 0x80000000 and 0x10000000 -> 7FFFFFFFF is not used)

I then used a flyswatter2 and openocd tcl script to perform the DCD initializations. (attached to this email)

 

Am I supposed to reduce the clock speed before setting the DCD settings? ( I don’t see this done in any of your sample code but the LPDDR2 spec says something of the sort should be done)

Also I am unable to execute the following due to JTAG-DP STICKY ERROR

# Switch PL301_FAST2 to DDR Dual-channel mapping

mww 0x00B00000 0x1

 

What could be causing my reads to be corrupt? Could this be a delay/calibration issue? I have played around with my delay and impedance settings but am having the same issue.

 

Your input would be much appreciated

Thanks

Original Attachment has been moved to: lpddr2_mmdc_dcd_settings.txt.zip

Original Attachment has been moved to: jtag_init_script.cfg.zip

Labels (4)
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3 Replies

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Yuri
NXP TechSupport
NXP TechSupport

I am afraid the i.MX6Q supports only dual-channel LPDDR2 (both CS0 and CS1 are active).

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aven_tsao
NXP Employee
NXP Employee

The dual channel mode only support LPDDR2 device, but the signal channel mode support both LPDDR2 and DDR3.

In this case, it should use signal channel mode.

Best regards

Aven

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aven_tsao
NXP Employee
NXP Employee

Please use signal channel mode, and the reference dram setting is attached

Best regards

Aven