Hi Alejandro,
Thank you for the support.
Each of the displays will have dual-Link LVDS interface(8 data pairs, 2 clock pairs).
The two RGB ports of the iMX6-SCM will be used with the RGB to dual-LVDS bridge chips.
The LVDS. The maximum LVDS clock frequncy can go 148 MHz for 1080x1920p @ 60fps.
The iMX6-SCM also has LVDS port which can be used directly for one of the displays.
But in that case for the other display we will have to use the bridge chip, which may require some sync mechanism if we want to achieve concurrency for both the displays.
Please give your suggestions on such implementation. And what things we must take care in such situations.
Also, we are about to start the design based around ths iMX6-SCM, so we will need NXP's support for design review and to solve some of our queries. Can we have some specific point of contact for this.
Thanks,
Nimesh Kotak.