iMX6 - DDR3 configuration/initialization: kernel or bootloader?

[arielhernandez]

Hi! I have a question about DDR3 configuration/initialization with iMX6 Dual/Quad. I'm not sure if this configuration has to set in the bootloader, kernel or both!

In this post https://community.freescale.com/thread/305189 Favio wrote that the kernel uses whatever the bootloader has configured. It seems that the iMX6 and iMX5 have the same configuration, but I want to be sure.

Can somebody help me with this?

Thanks!

Ariel.

[AnsonHuang]

Hi, Ariel

     Let me explain all the DDR config's location. In uboot, take v2009.08 for example, i.MX6Q SabreSD board, the DDR config is in board/freescale/mx6q_sabresd/flash_header.S, which will initi DDR controller and DDR chip, then the DDR size is defined in include/configs/mx6q_sabresd.h, PHYS_SDRAM_1. Uboot will pass this size parameter to kernel, and kernel will just use it.

     What do you mean by iMX6 and iMX5 have same configuration? do you mean the DDR config or size config? DDR config must be different, as their controller are different, size may be same, as they may have same DDR size.

[arielhernandez]

Yongcai Huang,

Thank you so much for your clarification. I mean the DDR configuration, I made several test with Wandboard and Sabreboard and I figured out that the memory size parameter is set in U-boot.

But, I can't understand why the LPDDR2 has a Device Tree bindings in the kernel and DDR3 hasn't. I'm trying to learn how to and where configure a DDR3 memory. Can you explain something of this?

I was found a LPDDR2's configuration in Device Tree of, for example, the Pandaboard (elpida), but nothing about DDR3, I guess the kernel has a power managment of a LPDDR2 memory. Is there another reason for this?

Thanks again!!

Regards,

Ariel.

[AnsonHuang · Accepted solution]

Thank you so much for your clarification. I mean the DDR configuration, I made several test with Wandboard and Sabreboard and I figured out that the memory size parameter is set in U-boot.

But, I can't understand why the LPDDR2 has a Device Tree bindings in the kernel and DDR3 hasn't. I'm trying to learn how to and where configure a DDR3 memory. Can you explain something of this?

[Anson] Which device tree you saw the LPDDR2 config? We did NOT have such config on i.MX6SL which uses LPDDR2.

I was found a LPDDR2's configuration in Device Tree of, for example, the Pandaboard (elpida), but nothing about DDR3, I guess the kernel has a power managment of a LPDDR2 memory. Is there another reason for this?

[Anson] Can you give an example of the dts? different platform may have different solution for memory config, but if kernel is running at ddr, then re-initialize ddr config is very complicated, that is why uboot always have this done. For our i.MX6, in kernel, we can scale DDR's freq, which is called bus freq.

Thanks again!!

[arielhernandez]

Perfect!! Question answered!

Thank you so much!

Ariel.