Hello
Could someone provide guidance on how to set up the l2 cache on the iMX53. We are using it in a bare metal application and need to configure the l2 cache. Using uBoot as a guide I was able to get working but performance is less than expected. Here is what is written to the L2 cache aux control register:
;reconfigure L2 cache aux control reg */
mov r0, #0xc0 ;tag RAM
add r0, r0, #0x4 ;data RAM was
orr r0, r0, #(1 << 24) ;disable write allocate delay
orr r0, r0, #(1 << 23) ;disable write allocate combine
orr r0, r0, #(1 << 22) ;disable write allocate
orr r0, r0, #0x20 ;L1 neon on
cmp r3, #0x10 ;r3 contains the silicon rev
;disable write combine for TO 2 and lower revs
orrls r0, r0, #(1 << 25)
mcr p15, 1, r0, c9, c0, 2 ; Write L2 Cache Auxiliary Control Register
I have a few questions:
1) are the latency values correct for iMX53
2) I believe the disable features following are required for errata workarounds is this correct
3) Am I missing anything else
Thanks
Joseph.walczyk@honeywell.com
