iMX 8M Nano Ultralite SAI Multi-Line Channel Mixups

[evancornell]

We have a custom board using i.MX 8M Nano Ultralite (MIMX8MN5DVPIZAA). 

It uses 5 SAI data pins for receiving audio data:

SAI5_RXD0 (left channel is AIN1, right channel is AIN2)

SAI5_RXD1 (left channel is AIN3, right channel is unused)

SAI5_RXD2 (left channel is HS1, right channel is HS2)

SAI2_RXD0 (left channel is AIN4, right channel is AIN5)

SAI2_RXD1 (left channel is AIN6, right channel is unused)

SAI5_MCLK, SAI5_RXC, SAI5_RXFS are all clock outputs (master mode). The custom board has all three of these signals fed back into the corresponding signals on SAI2, thus, SAI2 is operating in clock slave mode.

When doing the following arecord command:

arecord -D plughw:0,0 -f S32_LE -r 48000 -c 6 -B 30000000 testsai5_48k.wav

And feeding signals in sequence to AIN1, AIN2, and AIN3 inputs, the resulting 6 channel wav file actually has the audio show up in the following sequence:

Wav Ch / AIN signal

1 / AIN1

2 / AIN3

3 / blank

4 / AIN2

5 / blank

6 / blank

We were expecting to have this result:

1 / AIN1

2 / AIN2

3 / AIN3

4 / blank

5 / blank

6 / blank

When doing the following two arecord commands to capture SAI2 data pins:

arecord -D plughw:0,0 -f S32_LE -r 48000 -c 6 -B 30000000 /dev/null &    (This command just to provide clocks from SAI5 for SAI2)

arecord -D plughw:1,0 -f S32_LE -r 48000 -c 4 -B 30000000 testsai2_48k.wav

And feeding signals in sequence to AIN4, AIN5, and AIN6 inputs, the resulting 4 channel wav file actually has the audio show up in the following sequence:

Wav Ch / AIN signal

1 / AIN4

2 / AIN6

3 / AIN5

4 / blank

We were expecting to have this result:

1 / AIN4

2 / AIN5

3 / AIN6

4 / blank

We have been able to re-map the observed channels into the order we ultimately want by using an alsa configuration, but we need to understand why, even below alsa, the channels aren't coming in the order we expect. 

Our DTS has SAI5 correspond to soundcard plughw:0,0 and SAI2 corresponding to soundcard plughw:1,0. 

The SAI DTS entries are excerpted here:

&sai5 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai5>;
assigned-clocks = <&clk IMX8MN_CLK_SAI5>;
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
assigned-clock-rates = <49152000>;
clocks = <&clk IMX8MN_CLK_SAI5_IPG>, <&clk IMX8MN_CLK_DUMMY>,
<&clk IMX8MN_CLK_SAI5_ROOT>, <&clk IMX8MN_CLK_DUMMY>,
<&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_AUDIO_PLL1_OUT>,
<&clk IMX8MN_AUDIO_PLL2_OUT>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
fsl,sai-multi-lane;
fsl,sai-asynchronous;
fsl,dataline = <1 0x07 0x00>;
status = "okay";
dmas = <&sdma2 8 25 0>, <&sdma2 9 25 0>;

};

&sai2 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clk IMX8MN_CLK_SAI2>;
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
clocks = <&clk IMX8MN_CLK_SAI2_IPG>, <&clk IMX8MN_CLK_DUMMY>,
<&clk IMX8MN_CLK_SAI2_ROOT>, <&clk IMX8MN_CLK_DUMMY>,
<&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_AUDIO_PLL1_OUT>,
<&clk IMX8MN_AUDIO_PLL2_OUT>;
assigned-clock-rates = <49152000>;
fsl,sp-slave-mode;
fsl,sai-asynchronous;
status = "okay";
fsl,dataline = <1 0x03 0x00>;
fsl,sai-multi-lane;
dmas = <&sdma2 2 25 0>, <&sdma2 3 25 0>;

};

pinctrl_sai5: sai5grp {
fsl,pins = <
MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
MX8MN_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6
MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6
MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6
MX8MN_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1    0xd6
MX8MN_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2    0xd6

>;
};

pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MN_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x0
MX8MN_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x0
MX8MN_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0xd6
MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
MX8MN_IOMUXC_SAI3_RXC_SAI2_RX_DATA1 0xd6

>;
};

sdma2: dma-controller@302c0000 {
compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma";
reg = <0x302c0000 0x10000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
<&clk IMX8MN_CLK_SDMA2_ROOT>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
};

Can anyone identify the root cause of the behavior we're observing?

[Sanket_Parekh]

Hello @evancornell ,

I hope you are doing well.

->This is because the SAI controller is configured to use a different channel order than the physical pin connections. The channel order that is used by the SAI controller is defined in the DTS file.

->One needs to change the channel order in the DTS files for SAI5 and SAI2 to match the physical pin connections. After that, it should work in the order.

->Please check by adding the below line in the dts file of the sai node.
fsl,sai-channel-map = <0 1 2 3 5 4>;

->Once updated the DTS files, Please rebuild the kernel and boot loader.
I hope this helps!

Thanks & Regards,
Sanket Parekh

[evancornell]

Sanket,

Thanks for your reply. Can you please provide example reference code showing usage of that parameter? We are not seeing where that parameter usage affects lower-level driver settings.

Thanks,
Evan

[Sanket_Parekh]

Hello @evancornell ,

I hope you are doing well.
Please accept my apology for the inconvenience.

Please refer to the location given below for channel mapping.
Documentation/sound/alsa/Channel-Mapping-API.txt

One can also refer this link given below
https://community.nxp.com/t5/i-MX-Processors/Multi-Lane-SAI/m-p/1353481#M181355

It will help you!

Thanks & Regards,
Sanket Parekh