iMX.6 NAND: can BCH be disabled?

[_timm]

Hi, 

We are using a custom designed SoC with a iMX6D and a NAND device with built-in 4-bit ECC. Since we are not using the NAND as a filesystem, and don't expect to incur many bit errors due to wear, we would like to use the built-in 4-bit ECC mechanism in the NAND device, and disable the BCH in the iMX6. It is thought that this would increase the read/write speed, which are currently not good. I have modified the appropriate fields in the FCB that gets written to the NAND device, and also the Layout registers. I have also modified the read and write methods so that they do not set the ECC control fields in the descriptor chains. The SoC does not boot. Is there anything that I am missing here? Does Block 0 need to be set to ECC level 1 or some edge case that I am forgetting. I've reviewed the documentation, and haven't found the case described to turn off the BCH. 

Assistance is much appreciated. Thank you. 

Best Regards,

Tim Meese

[Yuri]

Hello,

  when using a NAND device with built-in ECC - it may be possible to modify Linux / U-boot drivers 

to support such feature, but i.MX boot ROM cannot be changed, therefore boot with such 

NAND will provide problems.

Regards,

Yuri.

[_timm]

Thanks, Yuri. 

I tried setting all of the ECC levels in the BCH to zero, set the BCH values in the FCB structure to zero. I then booted the bootrom into RAM, erased the entire part, and wrote the FCB and bootrom. The system did not boot. Is is that I cannot specify 0 as an ECC level in the FCB, or if I do, do I have to do something else? 

Thanks,

Tim Meese

[Yuri]

Hello,

  i.MX boot ROM configures the GPMI registers - hardly it may be "workarounded".

Regards,

Yuri.

[b36401]

You can use raw NAND for such purposes.

By the way here is a document regarding to performance comparation:
https://community.nxp.com/docs/DOC-334290

Have a great day,
Victor

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