i.mx6 question

[todtodf]

Dear  Expert:

In the i.mx6ull-evk board,I see this signal ENET1_nRST of KSZ8081 is from 74LV595PW(the driver input source is  SNVS_TAMPER7&SNVS_TAMPER8 of imx6ull)

If I want to use the i.mx6ull other gpio to control ENET1_nRST,what code should i modify?

I use L4.1.15 linux.

please give me help,thanks.

BRs

Tod

[weidong_sun]

Hello tod,

     74LV595PW is I2C to GPIO expender ( I2C to 6 channel GPIO). if you want to use a PINs of processor directly to control reset of Phy.

     you should do steps below:

(1) IOMUX in device tree

For exmaple, Useing PAD "NAND_CE0" to control reset of phy,  open "imx6ul-pinfunc.h", and found:

#define MX6UL_PAD_NAND_CE0_B__GPIO4_IO13                          0x01AC 0x0438 0x0000 0x5 0x0

so add "MX6UL_PAD_NAND_CE0_B__GPIO4_IO13"  to  imx6ull-14x14-evk.dts

...

    imx6ul-evk {
        pinctrl_hog_1: hoggrp-1 {
            fsl,pins = <
                MX6UL_PAD_UART1_RTS_B__GPIO1_IO19    0x17059 /* SD1 CD */
                MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 /* SD1 VSELECT */
                MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */

                MX6UL_PAD_NAND_CE0_B__GPIO4_IO13      0x17059 /* PHY reset*/
            >;
        };

...

(2) Add it to fec1

In imx6ull-14x14-evk.dts:

&fec1 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_enet1>;
    phy-mode = "rmii";

    phy-reset-gpios = <&gpio4 13 0>;
    phy-handle = <&ethphy0>;
    status = "okay";
};

Have a great day,
TIC   Weidong sun

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[todtodf]

Dear  Expert:

thanks for your support.

Could you help answer the questions below:

1. phy-reset-gpios = <&gpio4 13 0>;    

here what does "0" mean?

2.74LV595PW is I2C to GPIO expender ( I2C to 6 channel GPIO)

About the reset phy function,where is the code(control 74LV595 to reset phy)?

BRs

Tod