[i.mx25] will clock adjusting occur SDRAM memory corruption.

[王剑翰]

Dear,

Could you help to confirm why does the memory corruption occure after the clock adjusting?

Is there any wrong sequence for below code architecture?

[Using environment]
CPU　i.MX25
SDRAM K4T51163QI-HCE6

[Failure mode]

Boot1

     1. Initialize SDRAM

     2. Change clock: core  133Hz  DRAM 66.5Hz

     3. Initialize Nand Flash

     4. Read bin file of Boot2 from Nand Flash to SDRAM

     5. Jump to SDRAM， Run Boot2

Boot2

     1. Change ARM CPU mode to Supervisor

     2. Change clock core:  399Hz  DRAM 133Hz                               <--Memory corruption here（Memory corruption occures on 2 of 40 machines occasionally)

     3. Run library function of IAR, Prepare environment for user main      <--Program crash for memory corruption.

     4. Run user's main function

Thank you!

[art]

Any SDRAM bus frequency change when SDRAM is in operational mode can cause some unpredictable behaviour of the SDRAM. The right sequence of doing this is as follows.

1. Put SDRAM to Self-Refresh mode.

2. Change the bus frequency.

3. Switch SDRAM back to operational mode.

Have a great day,
Artur

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[王剑翰]

Dear,

Beside, if we do not change the clock, then no memory corruption was found. So, can the clock frequence be adjusted when the SDRAM is working? If not, pls also help share the reason.

Thanks!

Jianhan Wang