Hi,
I'm using the i.MX6ULL processor, and I've setup the ecspi 1 in burst transmission mode, with 32 bits-per-word and a burst length of 128 words. However, I'm only needing to send 240 bytes in a single burst transmission. The data output is clocked at 3.45 MHz.
The issue I'm seeing in the data packet is an occasional (although seemingly periodic) gap in the transmission. This gap will always be around 1usec in length, and its a delay that is present on the MOSI data and spi clock (indicating the data didn't get changed or corrupted). A screen-capture of this delay is provided.
My 240 byte burst transmission works as intended for a majority of the time, but perhaps ~1/4 of the time this delay will occur within the packet messing up the timing. The DMA for the SPI is being setup and used here. Is it correct for me to think my SPI settings aren't the issue since it works without interruption a portion of the time? What would be causing this; is it possible for something else to be interrupting the SPI even with the DMA handling the buffer transfer?
Thanks.
Hello,
Perhaps the problem concerns eCSPI FIFO underflow issue.
Regards,
Yuri.
Hi Yuri,
Could you explain that idea a bit more? I don't think I'm too familiar with FIFO underflow issues as mentioned.
Thanks,
Alex
Hi, alexhinton
When DMA is used and FIFO achieves its threshold level, the DMA requests access to memory
in order to read a burst of data to the FIFO. If such request is not served in time (because of system
busy) the situation of underflow takes place.
Regards,
Yuri.
Yuri,
Thanks for the additional explanation, that helps me better understand this. Is there something I can do to confirm this is whats causing the delay? Considering this to be the case, what can be done to try and fix or mitigate it?
Regards,
Alex
Hello,
perhaps this is a performance issue. If possible - try to increase priority of the application,
decrease other loads (remove additional bus throughput consuming tasks).
Regards,
Yuri.