i.MXRT117x eDMA possible problem

[jernejturnsek]

Hi all,

I am reading external ADC with the help of FlexIO and DMA peripheral to get samples into memory. I have configured FlexIO2 peripheral to generate FS and CLK signal to ADC and read 8 channels in TDM mode with the help of shift register in FlexIO. Single shift register is generating DMA request to channel 0 of the eDMA and after 32 samples times 8 channels is received an interrupt is generated to process the samples. eDMA is configured in ping-pong mode with the single descriptor, where half-interrupt and done-interrupt is used. After done interrupt is triggered, eDMA is automatically resetting the destination address to the beggining of a buffer. Interrupt routine of the eDMA driver is inspecting DONE flag and it is triggering user callback function with the status of the DONE flag. User callback interrupt is then looking into this status attribute to decide from which part of the buffer it should read 32 samples. Becuase I am using NuttX OS, I am scheduling HP Work Queue in every interrupt after every 32 samples is received. This HP work queue task is then resampling and scheduling LP Work Queue for FFT processing.

The problem is when I am not scheduling LP Work queue, eDMA interrupts are working as they should, no problem at all. But when LP Work Queue is used ( CPU processing is increased substantially), eDMA interrupts are still triggered periodically (without jitter), but DONE flag is SOMETIMES not set in eDMA, resulting in my interrupt service callback routine not reading proper buffer. With the help of a debugger I have found out that at the time of interrupt destination register is already ahead a few words (maybe due to some delay between interrupt occuring and interrupt processing) and maybe this is the reason the DONE flag is not set properly?

When I am using my own toggling logic (simple toggle variable), things work like a charm. But my solution is not the best one, because in the case of desinhronization, things would go wrong very fast. I could maybe use two DMA descriptors linked together, but nevertheless I would like to understand what is going one with single descriptor solution. Anyone?

Regards,

Jernej

[Bio_TICFSL]

Hello,

We recommend customer to use MCUXpresso SDK software package for RT1170 product, which provides eDMA driver and related examples (including memory to memory copy).

RT1170's eDMA IP is original from Kinetis product platform, I searched below eDMA training materials for your reference.

Wish it helps.

eDMA for Kinetis K series MCUs

Example code on how to use DMA in Kinetis® K60

Regards

[jernejturnsek]

Hi,

I am aware of MCUXpresso SDK and I have checked for this case the examples, but I didn't find one. Also went through documentation and I do not see anything wrong with my code. Here is my excerpt of code how to set things up (I know it is NuttX driver, but the important stuff is clearly visible): 

struct imxrt_edma_xfrconfig_s config;

config.saddr = flexio->ops->get_shifter_buffer_address(flexio, FLEXIO_SHIFTER_BUFFER_BIT_SWAPPED, FLEXIO_RX_SHIFTER_INDEX);
config.daddr = (uint32_t)&dmarxbuf[0];
config.soff = 0;
config.doff = 4;
config.iter = 512;
config.flags = EDMA_CONFIG_LINKTYPE_LINKNONE |
EDMA_CONFIG_LOOPDEST |
EDMA_CONFIG_INTHALF |
EDMA_CONFIG_INTMAJOR;
config.ssize = EDMA_32BIT;
config.dsize = EDMA_32BIT;
config.nbytes = 4;

imxrt_dmach_xfrsetup(priv->rxdma, &config);

My destination buffer is in uncached section. What is different from examples, is LOOPDEST flag, where destination address is looped back to begining. What I am asking here, is there a possibility that DONE interrupt is triggered and DONE flag is cleared by hardware, if interrupt is not serviced imedialtely? This is my only explanation of what I am seeing im my case.

Another weird thing I am seeing here is, when I put my dma rx buffer into uncached section (i.e. OCRAM_ECC), DMA is reading correct data, but if I put it into DTCM (which is also uncached), I do not get valid data.