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i.MX93 RMII Device Tree Example

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i.MX93 RMII Device Tree Example

‎07-10-2024 12:41 PM
503 Views
tim_cargt
Contributor II

I am creating a custom PCBA based on the #iMX93. I want to configure the EQOS and FEC to both use RMII mode generating the 50 MHz clock to the PHY as described in this document. 

I am running Yocto Mickledore (6.1.55).

When I modified my device tree (based on the i.MX93 11x11 EVK) per the document above, the generated clocks run at 250 MHz instead of 50 MHz.

Are there any device tree examples showing how to configure the FEC and EQOS clocks for RMII operation?

From imx93.dtsi (unmodified):

			fec: ethernet@42890000 {
				compatible = "fsl,imx93-fec", "fsl,imx8mp-fec", "fsl,imx8mq-fec";
				reg = <0x42890000 0x10000>;
				interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_ENET1_GATE>,
					 <&clk IMX93_CLK_ENET1_GATE>,
					 <&clk IMX93_CLK_ENET_TIMER1>,
					 <&clk IMX93_CLK_ENET_REF>,
					 <&clk IMX93_CLK_ENET_REF_PHY>;
				clock-names = "ipg", "ahb", "ptp",
					      "enet_clk_ref", "enet_out";
				assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>,
						  <&clk IMX93_CLK_ENET_REF>,
						  <&clk IMX93_CLK_ENET_REF_PHY>;
				assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
							 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>,
							 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
				assigned-clock-rates = <100000000>, <250000000>, <50000000>;
				fsl,num-tx-queues = <3>;
				fsl,num-rx-queues = <3>;
				fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>;
				status = "disabled";
			};

			eqos: ethernet@428a0000 {
				compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a";
				reg = <0x428a0000 0x10000>;
				interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "eth_wake_irq", "macirq";
				clocks = <&clk IMX93_CLK_ENET_QOS_GATE>,
					 <&clk IMX93_CLK_ENET_QOS_GATE>,
					 <&clk IMX93_CLK_ENET_TIMER2>,
					 <&clk IMX93_CLK_ENET>,
					 <&clk IMX93_CLK_ENET_QOS_GATE>;
				clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
				assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>,
						  <&clk IMX93_CLK_ENET>;
				assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
							 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
				assigned-clock-rates = <100000000>, <250000000>;
				intf_mode = <&wakeupmix_gpr 0x28>;
				clk_csr = <0>;
				nvmem-cells = <&eth_mac2>;
				nvmem-cell-names = "mac-address";
				status = "disabled";
			};

From my custom device tree:

 

 

&eqos {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_eqos>;
	phy-mode = "rmii";
	phy-handle = <&adin1100>;
	snps,reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
	snps,reset-delays-us = <10 20 200000>;
	status = "okay";

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;

		adin1100: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			interrupt-parent = <&gpio4>;
			interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
		};
	};
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	phy-mode = "rmii";
	phy-handle = <&ethphy2>;
	fsl,magic-packet;
	phy-reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <10>;
	phy-reset-post-delay = <150>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy2: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
			eee-broken-1000t;
		};
	};
};
...
	pinctrl_eqos: eqosgrp {
		fsl,pins = <
			MX93_PAD_ENET1_MDC__ENET_QOS_MDC						0x57e
			MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO						0x57e
			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0					0x57e
			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1					0x57e
			MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER						0x5fe
			MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x57e
			MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0					0x57e
			MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1					0x57e
			MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x40000b16
			MX93_PAD_ENET1_TXC__ENET_QOS_TX_ER						0x5fe
			MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x57e
			MX93_PAD_ENET1_RD3__GPIO4_IO13							0x31e // T1L_NRST
			MX93_PAD_ENET1_RD2__GPIO4_IO12							0x31e // T1L_INT
		>;
	};

	pinctrl_fec: fecgrp {
		fsl,pins = <
			MX93_PAD_ENET2_MDC__ENET1_MDC					0x57e
			MX93_PAD_ENET2_MDIO__ENET1_MDIO					0x57e
			MX93_PAD_ENET2_TD2__ENET1_TX_CLK				0x4000057e			
			MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1				0x57e
			MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0				0x57e
			MX93_PAD_ENET2_TXC__ENET1_TX_ER 				0x57e
			MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL		0x57e
			MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL		0x57e
			MX93_PAD_ENET2_RXC__ENET1_RX_ER 				0x57e
			MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0				0x57e
			MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1				0x57e
			MX93_PAD_ENET2_RD3__GPIO4_IO27					0x31e // ETH_NRST
		>;
	};

 

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3 Replies

‎07-12-2024 01:26 PM
449 Views
tim_cargt
Contributor II

I was able to get RMII working with both EQOS and FEC using information from AN14149. I did need to modify the MDIO clock divider  (clk_csr) in the .dtsi file after making changes to get the EQOS to generate the 50 MHz reference clock. The MDC was running at about 7.5 MHz instead of 2.5 MHz before adjusting the clk_csr setting.

For reference, here are my device tree settings:

From imx93.dtsi (now modified):

			fec: ethernet@42890000 {
				compatible = "fsl,imx93-fec", "fsl,imx8mp-fec", "fsl,imx8mq-fec";
				reg = <0x42890000 0x10000>;
				interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_ENET1_GATE>,
					 <&clk IMX93_CLK_ENET1_GATE>,
					 <&clk IMX93_CLK_ENET_TIMER1>,
					 <&clk IMX93_CLK_ENET_REF>,
					 <&clk IMX93_CLK_ENET_REF_PHY>;
				clock-names = "ipg", "ahb", "ptp",
					      "enet_clk_ref", "enet_out";
				assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>,
						  <&clk IMX93_CLK_ENET_REF>,
						  <&clk IMX93_CLK_ENET_REF_PHY>;
				assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
							 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>,
							 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
				assigned-clock-rates = <100000000>, <50000000>, <50000000>;
				enet_clk_sel = <&wakeupmix_gpr 0x2C>;
				fsl,num-tx-queues = <3>;
				fsl,num-rx-queues = <3>;
				fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>;
				status = "disabled";
			};

			eqos: ethernet@428a0000 {
				compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a";
				reg = <0x428a0000 0x10000>;
				interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "eth_wake_irq", "macirq";
				clocks = <&clk IMX93_CLK_ENET_QOS_GATE>,
					 <&clk IMX93_CLK_ENET_QOS_GATE>,
					 <&clk IMX93_CLK_ENET_TIMER2>,
					 <&clk IMX93_CLK_ENET>,
					 <&clk IMX93_CLK_ENET_QOS_GATE>;
				clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
				assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>,
						  <&clk IMX93_CLK_ENET>;
				assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
							 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
				assigned-clock-rates = <100000000>, <50000000>;
				intf_mode = <&wakeupmix_gpr 0x28>;
				enet_clk_sel = <&wakeupmix_gpr 0x2C>;
				clk_csr = <5>;
				nvmem-cells = <&eth_mac2>;
				nvmem-cell-names = "mac-address";
				status = "disabled";
			};

 

From my custom device tree:

&eqos {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_eqos>;
	phy-mode = "rmii";
	phy-handle = <&adin1100>;
	snps,reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
	snps,reset-delays-us = <10 20 200000>;
	status = "okay";
	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;
		adin1100: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
			interrupt-parent = <&gpio4>;
			interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
		};
	};
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	phy-mode = "rmii";
	phy-handle = <&ethphy2>;
	fsl,magic-packet;
	phy-reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <10>;
	phy-reset-post-delay = <150>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy2: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			eee-broken-1000t;
		};
	};
};

 

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‎07-16-2024 03:41 AM
400 Views
joanxie
NXP TechSupport
NXP TechSupport

what's your issue? and what imx93 dts you based on?  11x11 or 14x14? you couldn't get the clock what you need?

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‎07-11-2024 08:18 PM
466 Views
joanxie
NXP TechSupport
NXP TechSupport

I have updated to you for another same case, pls check

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