i.MX93 Power Off Sequence

[Michaelscott237]

Hello,

I am currently designing a custom board based on the i.MX93 and i'm working on my active discharge circuitry to ensure we meet the datasheet power-down requirements.

To validate my understanding, I performed measurements on the i.MX93 EVK (Board Rev: 700-51961 Rev B, SCH-51961 Rev B5, SOM B2).

According to the i.MX93 Data Sheet, the power-down sequence requires that BBSM rail is the last rail to be turned off.

What I came across:

When I unplug the USB-C power source or toggle the main power switch on the Base Board, the observed sequence does not seem to match the datasheet requirement.

Measurement Setup:

• CH1: SOC Rail (Measured at TP703)

• CH2: BBSM Rail (Measured at TP709)

Questions:

1. Is the EVK designed to support a managed power-down sequence during an abrupt power loss (e.g., unplugging USB), or is this requirement only strictly enforced during a software-initiated shutdown via the PMIC?

2. In my capture,  Could you explain why the EVK behavior deviates from the datasheet's power-down sequence requirement?

Thank you for your help!

[JorgeCas]

Hello,

This requirement only strictly enforced during a software-initiated shutdown via the PMIC, when you unplug the USB-C power cable, it shuts down all the power rails at the same time.

The behavior you are seeing is expected.

Best regards.

[Michaelscott237]

Thank you for the clarification. Since the EVK behavior is expected during a 'hard' power loss, i have a few follow-up questions:

1. Is then the power-down sequence requirement strictly for Data/RTC/Secuity State Integrity, or is there a risk of Long-Term Reliability issues or physical damage to the SoC if the rails coolapse simultaneously? (i.e, if i keep powering off my EVK, it will be damaged soon? because using the power switch is pretty common). Or if the SOC remains high while BBSM collapsed, is there a risk of internal diode biasing or latch-up conditions?

2. if niether, what is then really the purpose of doing this requirement via software also?

3. If the requirement is criticial for reliability, does NXP recommend specific total capactiance on the input rail to allow the PMIC enough 'hold-up' time to execute a sequenced shutdown?

and that will lead to another question: right now i'm trying to figure out how to set the i.MX to be the lowest power it can to reduce the current consumption for the active discharge process, but i can't seem to get the same results NXP measured for suspend mode for example (I get 12mA for SOC rail when i enter suspend mode via echo mem command and also 85mA for the VSYS_5V [PMIC INPUT] which seem alot)

[JorgeCas]

Hello,

1. It is recommended to follow the power-off sequence to avoid a current leakage or an irreversible damage to the processor/PMIC in the worst-case scenario. I have seen many cases where the power supply is disconnected and it does not cause any damage.

2. Is not needed to implement it in software.

3. Follow our EVK's power management solution is enough to warranty correct operation in Long-Term.

Regarding the power consumption I suggest you create another community post since we handle one topic per post. I can check it in your submitted ticket.

Best regards.

[Michaelscott237]

"It is recommended to follow the power-off sequence to avoid a current leakage or an irreversible damage to the processor/PMIC in the worst-case scenario"
Something i dont understand about that, in the evk as i just shown, it doesn't follow that recommendation,
So how it is okay to follow the evk solution?
Or you declare that on the case when you unplug the power, you dont have to follow the sequence requirements? It seems odd, then why should i follow it in the first place?
Software wise its easy to set the pmic for thr right sequence, but as i know, you gave that sequence for a reason for all cases...

[JorgeCas]

Hello,

These power sequence is followed when the processor is turned off by software, when you unplug the board is expected to see the all the regulators out turned off at the same time sin VSYS falls bellow the minimum operating range.

The i.MX93 EVK does not attempt to guarantee the datasheet power‑down sequence during an abrupt power loss, this requirement is only guaranteed during a PMIC‑managed, software‑initiated shutdown.

Best regards.

[Michaelscott237]

Okay i see,
I just want to make sure i understand correctly.
I try to follo this guideline from TI:
https://www.ti.com/document-viewer/lit/html/SSZTAP3
And from what you are saying, the i.mx doesn't need to be safe from this kind of operation (unexpected power off) so there is nothing to be worried about that and there is no need for extra considerations besides the software power off sequence and for the unexpected power off, all rails drop simultaneously which will not harm the cpu

[JorgeCas]

Hello,

Thank you for the information.

That is correct, PMIC's behavior regarding unplug the input power, it will turn-off al the regulators at the same time and this will not damage the device.

Best regards.

[Michaelscott237]

So why the power off sequence is needed in the first place, if there is a case where it will not damage the device?

[JorgeCas]

Hello,

It will not damage the device, this is an expected state that is described in PMIC's datasheet:

Off mode

PCA9451A enters OFF mode from any state when VSYS falls below VSYS_POR threshold. All regulators are off and all registers get reset in this mode.

Best regards.

[Michaelscott237]

But we are talking about the i.MX not the PMIC, we don't care what the states the PMIC can do, i care about my device im powering which is the processor. 

From the i.mX datasheet:

 it seems you do declare it can cause damage in worst case scenario, so i don't understand how come you are saying it's okay to power it down not according the sequence requirement.

Am i missing something? 

[JorgeCas · Accepted solution]

Hello,

After reviewing again with the internal team, the statement about “irreversible damage (worst‑case scenario)” applies mainly to power‑up sequence deviations. During power‑up, an incorrect supply order can cause over-current or back‑powering conditions that may electrically damage the processor.

For power‑down, the situation is different: all supplies are already at valid levels, and when power is removed (for example, unplugging the cable), the regulators and the processor simply collapse to 0 V. In this case, the same electrical stress mechanisms are not present, so the i.MX is not damaged even if the power‑down sequence is not strictly followed.

This is why a software-controlled shutdown is recommended (to finish running tasks and avoid data corruption if is the case in your application), but it is not an electrical requirement to protect the processor. The critical requirement to avoid hardware damage remains the correct power‑up sequence.

Best regards.