i.MX93 LPDDR4 Support for Dual-Rank Single-Channel Configuration

[ZigaB]

I am working on a new System-on-Module (SoM) design based on the i.MX93 processor. Due to the current volatility in the LPDDR4 memory market, we are looking for ways to increase our sourcing flexibility.

Specifically, we want to know if the i.MX93 DDR controller supports a Single-Channel, Dual-Rank configuration using two discrete LPDDR4 chips.

Our proposed setup:

• Topology: 16-bit Single-Channel.

• Configuration: Two x16 LPDDR4 chips sharing the same Address, Command, and Data bus.

• Selection: Utilizing separate Chip Select (CS0 / CS1) and Clock Enable (CKE0 / CKE1) lines for each chip to form two ranks.

This would allow us to populate the board with either:

1. 1x 2GB LPDDR4 (Single-Rank) or

2. 2x 1GB LPDDR4 (Dual-Rank, using the same PCB footprint/layout logic).

Questions:

1. Does the i.MX93 DDR controller silicon and the official firmware (DRAM initialization/training) support Dual-Rank configurations for LPDDR4?

2. Are there any specific layout constraints or signal integrity concerns we should be aware of?

3. Are there any known limitations in the Config Tools for setting up Dual-Rank timing parameters for this processor?

Thank you for your assistance and technical insights.

[pengyong_zhang]

Hi @ZigaB 

1. Does the i.MX93 DDR controller silicon and the official firmware (DRAM initialization/training) support Dual-Rank configurations for LPDDR4?

>>> i.MX93 can support 2 ranks dram.

1. Are there any specific layout constraints or signal integrity concerns we should be aware of?

>>>You can refer to the section titled “3.6 DDR Design Recommendations” in the imx93 HDG document.

1. Are there any known limitations in the Config Tools for setting up Dual-Rank timing parameters for this processor?

>>>Make sure  that the total DRAM capacity does not exceed 2 GB.

B.R

[db16122]

Please refer to the feedback below, BTW how many density do you need for LPDDR4, you can use 2GB x8 LP4 to reach 4GB if you like

1. Does the i.MX93 DDR controller silicon and the official firmware (DRAM initialization/training) support Dual-Rank configurations for LPDDR4? Since there are two chip select for DRAM interface, dual rank should be support

2. Are there any specific layout constraints or signal integrity concerns we should be aware of?  You can refer to TN-53-06: LPDDR4/LPDDR4X Point-to-Point Design Guidelines from MICRON for detail, capacitor placement for voltage supply pin and equal routing for DQS should be the key. Meanwhile you may contact memory vendor for TSA measurement timing and signal analysis need to double check from oscilliscope

3. Are there any known limitations in the Config Tools for setting up Dual-Rank timing parameters for this processor?  Config Tools for i.MX Applications Processors | NXP Semiconductors You may refer to the previous setting experience if possible