i.MX8ULP single channel LPDDR4X DDR Tool calibration fails

[PaulBudich1]

Hello, 

we are trying to get our custom i.MX8ULP board up and running. 
We are using a 4Gbit single Channel LPDDR4X DRAM (IM4G16L4JCBG-046)
Datasheet:Datasheet 

We filled the RPA excel sheet with data width 16, but when we upload the ds file in the DDR Tool it shows data width 32 and double the density. 
The Calibration fails with error(0x4), i also uploaded the full log-file. 

Also were not shure how to implement DataBusConfig for single channel, we only filled in DQ0-15, but then the formula in line 16 shows #NV and some registers in the DRR stress test file also. 
RPA excel sheet is also attached. 

[Lukas_LH]

@JorgeCas thanks for the fast response!
I am a colleague of Paul's. The error we are observing is to be expected and a secondary issue since we only have channel 1 connected with 16 data bits but the configuration generated by the RPA tool gets interpreted by the DDR Tool as dual channel 32bit config. Hence the training fails with a data bit mapping error.

Can you please let us know if the RPA tool is capable of generating a single channel 16bit bus configuration? (only channel A is used) Comparing the highlighted settings in the RPA tool with the log generated by the DDR tool it seems like the config genrated by the RPA tool does not correctly reflect a single channel implementation. (Data bus width of 32 does not match with the setting in the RPA tool and the total density is also double what we´ve parameterized in the RPA tool)
Please let us know how to correctly fill in the data bit mapping in the RPA tool when only a single channel is used and how the remaining empty fields for the unused channel should be treated.

Thank you!

[JorgeCas]

Hello,

I have an update from internal team:

Based on my analysis, I suspect that the LPDDR4X RPA does not correctly configure the 16-bit mode. Can you please manually modify the .ds file as follows:

From:

memory set 0x2E0603E8 32 0x00010000 # DENALI_CTL_250

To:

memory set 0x2E0603E8 32 0x01010000 # DENALI_CTL_250

and let me know if the data bus width gets correctly detected on your side?

Best regards.

[JorgeCas]

Hello,

I reproduced the issue in my side, as you mentions, the RPA does not update the bus width when changing to 16 bit.

Let me check if this configuration is not supported in i.MX8ULP/DDR tool.

Best regards.

[JorgeCas]

Hello,

Your error is caused by the data bit mapping.

Could you please share your LPDDR4X schematic section?

Best regards.