i.MX8QXP RMII Clock Frequency Adjustment for Ethernet Conformance Testing

[Divyansh_Rai]

Hi NXP Community,

I am working on a custom board based on the i.MX8QXP SoC. The Ethernet interface is configured in RMII mode, which, according to the reference manual, operates at 50 MHz. The Ethernet port is connected to a 10/100/1000 Atheros AR8031 PHY.

Support for the FEC Ethernet controller and the AR8031 PHY has been enabled in the kernel via the following configuration options:

• CONFIG_FEC

• CONFIG_AT803X_PHY

Below is the relevant section of our device tree configuration:

&fec1 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_fec_mdio>,
                <&pinctrl_fec1_gpio>,
                <&pinctrl_fec1>;
    clocks = <&enet0_lpcg 4>,
             <&enet0_lpcg 2>,
             <&clk IMX_SC_R_ENET_0 IMX_SC_C_DISABLE_50>,
             <&enet0_lpcg 0>,
             <&enet0_lpcg 1>;
    phy-mode = "rmii";
    phy-handle = <&external_ethphy>;
    phy-supply = <&reg_3v3_eth0>;
    phy-reset-gpios = <&lsio_gpio3 18 GPIO_ACTIVE_LOW>;
    phy-reset-duration = <1>;
    phy-reset-post-delay = <250>;
    digi,phy-reset-in-suspend;
    fsl,magic-packet;
    status = "okay";

    mdio {
        #address-cells = <1>;
        #size-cells = <0>;

        external_ethphy: ethernet-phy@1 {
            compatible = "ethernet-phy-ieee802.3-c22";
            smsc,disable-energy-detect;
            reg = <1>;
            /* max-speed = <100>; */
            /delete-property/ at803x,eee-disabled;
            /delete-property/ at803x,vddio-1p8v;
        };

        internal_ethphy: ethernet-phy@2 {
            compatible = "ethernet-phy-ieee802.3-c22";
            smsc,disable-energy-detect;
            reg = <2>;
            max-speed = <100>;
            /delete-property/ at803x,eee-disabled;
            /delete-property/ at803x,vddio-1p8v;
        };
    };
};

The Ethernet functionality is generally working as expected. However, during Ethernet Conformance Testing, some tests are failing due to slight deviations in the RMII reference clock frequency.

I would like to explore whether it is possible to slightly adjust the RMII clock—e.g., to 50.0005 MHz—to see if this helps pass the conformance tests. I understand that arbitrary clock frequencies may not be feasible due to PLL constraints and the use of integer dividers. Furthermore, the i.MX8QXP Reference Manual indicates that clock generation (especially for RMII) is managed by the System Controller Firmware (SCFW), and such clocks cannot be directly modified by software running in the OS.

Please suggest how we can adjust the RMII clock frequency through software in this setup.

Thanks,

Divyansh

[JosephAtNXP]

Hi,

Thank you for your interest in NXP Semiconductor products,

As said, you cannot modify the clocks or would be really hard, normally customers are advised to match as much as possible all the signals for same arrival time, after that, they tune skew with the following DTS properties.

tx-internal-delay-ps: enum: [0, 2000]

rx-internal-delay-ps: enum: [0, 2000]

If you would require to change specifically RMII, it's feasible to use external clock generators.

Regards