i.MX8MP WDT reset cause update issue

[titusstalin]

Hi,

I am trying to get reset cause event in imx8mp board and failed to get so.

I can see rebooting once WDT timeout (different value configured and can see CPU reset, booting uboot etc.,) occurred but 'reset_cause' is always as 'POR' and wondering how this could happen.

I have disabled systemctl stuff and did init=/bin/bash after kernel booted so nothing resets CPU before/after WDT timeout. Also I tried to read WDT reset_cause (SRSR) register in multiple places (SPL, Uboot) of uboot and still unable to get correct reset cause, always 0x1 which is CPU POR. Also ensured that SRSR register is not cleared after boot to retain the reset cause.

What could be the issue ? am i missing any patch or anything or could be HW bug ?
any pointers would be appreciated.

Thanks.

[Bio_TICFSL]

Hello,

Is the watchdog section (2.11) in the i.MX Linux Reference Manual applicatble to the i.MX8mp.  From what I have read it is not.

--> Yes, you can refer this. The i.MX8MP uses imx2-wdt.c driver.

The following IOCTLs are supported in the WDOG driver:
• WDIOC_GETSUPPORT
• WDIOC_GETSTATUS
• WDIOC_GETBOOTSTATUS
• WDIOC_KEEPALIVE
• WDIOC_SETTIMEOUT
• WDIOC_GETTIMEOUT
For detailed descriptions about these IOCTLs, see Documentation/watchdog.

Also please check:

https://community.nxp.com/t5/i-MX-Processors/i-MX8MP-Reset-Cause-POR/m-p/1328685

Regards

[titusstalin]

Thanks for your reply. And what you shared forum link is helpful.

Yes, I have also tested through Linux WDT ioctl to get watchdog status, but got 0 as POR reset which is NOT expected. I should see reset cause as 'WDT' reset.

As I mentioned, actually I am checking WDT status and reset_cause in uboot & SPL itself which is before Linux stage, so I don't think if uboot didn't update correct values in uboot we can't expect it in linux.

Also I made below dts change for not allowing PMIC to reset the CPU.

&wdog1 {
//fsl,ext-reset-output;
//pinctrl-names = "default";
//pinctrl-0 = <&pinctrl_wdog>;
status = "okay";
};

My humble request is that just once you go through the attached logs and re-read my post.

Thanks!

[opedis · Accepted solution]

NXP's support strikes me as mechanically copying some kind of drama script.
More like a desk lady who answers the phone.

Unfortunately this continues.

Anyway, here is my opinion: 

If you are using PMIC PCA9450 and that part of hardware design is the same as i.MX8MP evk. 

1. Monitor the PMIC POR_B of PCA9450. 

2. The wdog_b is remove/disable in dts, but still suggest to monitor that pin of PCA9450. 

[titusstalin]

Confirmed that WDT out pin is resetting the CPU.

[titusstalin]

Thanks for your support.

Yes, as I mentioned it I have disabled it in DTS but still got POR reset. Anyway as you recommended let me probe that pin and confirm.