i.MX8MP SAI Slave timing

[BertM]

We connect our CODECs to the I2S of the i.MX8MP, the i.MX8MP is I2S slave and so it receives the BCLK and FSync from an external source.

In the SAI Slave timing diagram I see that data IN sampling is related to the falling edge of BCLK, but sampling of the FSync IN is related to falling edge (setup) and rising edge (hold), see Doc: IMX8MPIEC (datasheet), Rev 2.1, Page 80, Figure 46, parameter S13 and S14.

Is this correct? And how does this match with the register description in the reference manual, see Doc: IMX8MPRM (Reference manual), Rev 2, Page 6038 / 6057, bit 25 BCP.

Thanks.

(snapshots added)

[Manuel_Salas]

Hello @BertM 

I hope you are doing well.

The timing for the I2S_FS signal (parameter S13 and S14) indicates that it is sampled and held around both the falling and rising edges of the BCLK.

BCP = 0

BCLK is active high, meaning data outputs are driven on the rising edge of BCLK, and inputs are sampled on the falling edge.

BCP = 1

BCLK is active low, with outputs driven on the falling edge, and inputs sampled on the rising edge.

The default configuration for BCP = 0 matches the diagram where data inputs are sampled on the falling edge see the S17.

However, I2S_FS is aligned with both edges of the BCLK, as indicated by the setup and hold parameters S13 and S14. This is independent of the BCP bit (Not controlled by polarity).

Best regards,

Salas.

[BertM]

Hello Alejandro,

Thank you for the explanation, so we must check setup/hold for rising and falling BCLK edge?

What is the rational behind this, can you explain briefly?

Best regards,

Bert