i.MX8MP LPDDR4 CA Training Failed (without it stress test is ok for single freq point)

[AlexandrP]

We designed a custom board based with

MIMX8ML8XXXKZ SoC

MT53E768M64D4DE-046 WT:C LPDDR4

BD71847 PMIC

All SoC and DRAM power lanes seem to be powered properly

Based on previous experience with i.MX8MM we attempted to generate timings for the DRAM using the DDR Mtool, but the result we got 

Spoiler

Download is complete
Waiting for the target board boot...

===================hardware_init=====================

hardware_init exit

*************************************************************************

*************************************************************************

*************************************************************************
MX8 DDR Stress Test V3.30
Built on Nov 24 2021 13:52:12
*************************************************************************

Waiting for board configuration from PC-end...

--Set up the MMU and enable I and D cache--
- This is the Cortex-A53 core
- Check if I cache is enabled
- Enabling I cache since it was disabled
- Push base address of TTB to TTBR0_EL3
- Config TCR_EL3
- Config MAIR_EL3
- Enable MMU
- Data Cache has been enabled
- Check system memory register, only for debug

- VMCR Check:
- ttbr0_el3: 0x97d000
- tcr_el3: 0x2051c
- mair_el3: 0x774400
- sctlr_el3: 0xc01815
- id_aa64mmfr0_el1: 0x1122

- MMU and cache setup complete

*************************************************************************
ARM clock(CA53) rate: 1800MHz
DDR Clock: 2000MHz

============================================
DDR configuration
DDR type is LPDDR4
Data width: 32, bank num: 8
Row size: 17, col size: 10
One chip select is used
Number of DDR controllers used on the SoC: 1
Density per chip select: 3072MB
Density per controller is: 3072MB
Total density detected on the board is: 3072MB
============================================

MX8M-plus: Cortex-A53 is found

*************************************************************************

============ Step 1: DDRPHY Training... ============
---DDR 1D-Training @2000Mhz...
PMU: Error: CA Training Failed.
PMU: ***** Assertion Error - terminating *****
[Result] FAILED

A similar situation was with the Config tool. We tried to use the .ds script both generated by Config tool, as well as the RPA, neither worked

Based on the discussion on the forum we attempted to disable the CA training. And calibration for single frequency setpoint started working

Spoiler

Download is complete
Waiting for the target board boot...

===================hardware_init=====================

hardware_init exit

*************************************************************************

*************************************************************************

*************************************************************************
MX8 DDR Stress Test V3.30
Built on Nov 24 2021 13:52:12
*************************************************************************

Waiting for board configuration from PC-end...

--Set up the MMU and enable I and D cache--
- This is the Cortex-A53 core
- Check if I cache is enabled
- Enabling I cache since it was disabled
- Push base address of TTB to TTBR0_EL3
- Config TCR_EL3
- Config MAIR_EL3
- Enable MMU
- Data Cache has been enabled
- Check system memory register, only for debug

- VMCR Check:
- ttbr0_el3: 0x97d000
- tcr_el3: 0x2051c
- mair_el3: 0x774400
- sctlr_el3: 0xc01815
- id_aa64mmfr0_el1: 0x1122

- MMU and cache setup complete

*************************************************************************
ARM clock(CA53) rate: 1800MHz
DDR Clock: 2000MHz

============================================
DDR configuration
DDR type is LPDDR4
Data width: 32, bank num: 8
Row size: 17, col size: 10
Two chip selects are used
Number of DDR controllers used on the SoC: 1
Density per chip select: 3072MB
Density per controller is: 6144MB
Total density detected on the board is: 6144MB
============================================

MX8M-plus: Cortex-A53 is found

*************************************************************************

============ Step 1: DDRPHY Training... ============
---DDR 1D-Training @2000Mhz...
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of read DQ deskew training
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 2D-Training @2000Mhz...
[Process] End of initialization
[Process] End of 2D write delay/voltage center optimization
[Process] End of 2D write delay/voltage center optimization
[Process] End of 2D read delay/voltage center optimization
[Process] End of 2D read delay/voltage center optimization
[Result] PASS

============ Step 2: DDR memory accessing... ============
Verifying DDR frequency point0@2000MHz.......Pass
[Result] OK

============ Step 3: DDR parameters processing... ============
[Result] Done

Success: DDR Calibration completed!!!

If multiple frequency setpoints are set, the optimization keeps failing at the second setpoint

And the stress test started passing correctly both in the Mtool and in the Config tool. However, the Diag read margin, diag write margin and CA eye tests keep failing

One thing to note is that comparing to the IMX8MP-EVK we connected the CA and CB to their respective pins on the CPU (in the EVK they were reversed)

Here are the respective lanes lengths and the delay deltas

Spoiler

1. CAx_B, CKE_A, CK_CS_A - 20mm, <1ps
2. CAx_B, CKE_B, CK_CS_B - 19mm, <1ps
3. DQ07_A - 15mm, <1ps
4. DQ07_B - 14.5mm, <1ps
5. DQ815_A -10mm, <1ps
6. DQ815_B -10mm, <1ps
7. CKA - 21mm, DQS0 - 15mm (-22ps to CKA), DQS1 - 13mm (-55ps to CKA)
8. CKB - 21mm, DQS2 - 14mm (-24ps to CKA), DQS3 - 13mm (-54ps to CKA)

Can the CA/CB swap be the reason of the problem?

[JorgeCas]

Hello,

Could you please share the connections of memory to i.MX device?

Best regards.

[sfatyushkin]

Hello @JorgeCas !

I am Alexander's colleague. Attached is the CPU and LPDDR connection diagram.

Best regards,
Serge

[JorgeCas]

Hello,

Your DDR connection is ok.

There is no functional problem in swap CA/CB since dual channel device channels are independent in LPDDR4, just keep in mind that bit swapping within each slice/byte lane is OK. Byte swapping is NOT allowed.

If you still having signal integrity tests failed, please look for layout issues and try lower operating frequencies.

You could try to change the tunning with different settings and check if helps with your design:

ODTImpedance

Desired ODT impedance in Ohm. Valid values for DDR4=240,120,80,60,40. Valid values for DDR3L=high-impedance,120,60,40. Valid values for LPDDR4=240,120,80,60,40

TxImpedance

Write Driver Impedance for DQ/DQS in ohm (Valid values for all DDR type= 240, 120, 80, 60, 48, 40, 34)

ATxImpedance

Write Driver Impedance for Address/Command (AC) bus in ohm (Valid values for all DDR type = 120, 60, 40, 30, 24, 20)

Best regards.

[AlexandrP]

Based on your response we decided to tackle the ODT parameters once again. We redid the Read/Write ODT and driver matrix in Optimization tab and noticed that some random ODT combinations drop 'Target a connection or exception in the script'. Saying random, I mean that from run to run they are different and don't occur every time. Otherwise, the rest of the combinations succeed, even up to 240 Ohm

We also evaluated the "Diag Read/Write Margin tests results more closely. Before, only the fact that test showed "checkmark 100%" was viewed , and noticed that whenever test "passes" it demonstrates not all of the DQ lanes, and the number is different every time. See attached pictures (for some reason the forum doesn't let me attach pictures neither in text, nor as attachments, so adding link to drive folder https://drive.google.com/drive/folders/1U4-G1_Em-73UR1zrtUFAsVCRBpAlchGN?usp=sharing)

Trying to investigate this, we observed the 1V1 power lane with the oscilloscope, didn't notice anything extra suspicious, but during that the "Diag Margin" test started to show the Eye diagrams for all of the DQ lanes in more or less okay shape, so we added 9.5pF capacitor (see the attachment with "cond" for reference), and the Margin Test results in all DQ lanes diagrams every time it shows anything

CA Bus Signals Margin test as well shows "Checkmark 100%", but in the "Charts" tab it states "Collecting diagnostic data..." and in logs it shows error "CA data is missing!" See full log in spoiler

Spoiler

#################### Result for: ca_bus ###### Run 1 ###############################################
Microsoft Windows [Version 10.0.19045.2965]
(c) Microsoft Corporation. All rights reserved.

C:\nxp\i.MX_CFG_25.03\bin>prompt test-prefix :

test-prefix : "C:/nxp/i.MX_CFG_25.03/bin/python3/python" "C:/nxp/i.MX_CFG_25.03/bin/python3/memtool/memtool_entry.py" -t "runtest" -d "C:/ProgramData/NXP/mcu_data_25.03/processors/MIMX8ML8xxxKZ/ksdk2_0/mem_validation/ddrc" -p "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy_training_ca_bus_lpddr4_0_0_.log" -i "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/figure_ca_bus_lpddr4_0_0_.png" -l DEBUG "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/connect.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/test.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_registers.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config_in.json"
INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/connect.json
INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/test.json
INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy.json
INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_registers.json
INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config.json
INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config_in.json
DEBUG memtool.common.factories new instance -> {inst}
DEBUG memtool.processor.base_processor freq_0 set to 667
INFO memtool.phyinit.phy_init Run phyinit for 2020.06\lpddr4
DEBUG memtool.phyinit.phy_init Shared library C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\phyinit\sharedlib\phyinit_2020.06_lpddr4.dll
DEBUG memtool.common.factories new instance -> {inst}
DEBUG memtool.phyinit.phy_init PHY config file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_config_final.json
DEBUG memtool.phyinit.phy_init Phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txt
DEBUG memtool.phyinit.phy_init Retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txt
DEBUG memtool.phyinit.out_parser Parse phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txt
DEBUG memtool.phyinit.out_parser Parse retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txt
DEBUG memtool.phyinit.out_parser Parse state A_BRING_UP_POWER
DEBUG memtool.phyinit.out_parser Parse state C_PHY_INIT_CONFIG(210)
DEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x32fb to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.c
DEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x15d4 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.json
DEBUG memtool.phyinit.out_parser Parse state LOAD_IMEM_1(445)
DEBUG memtool.phyinit.out_parser Parse state D_LOAD_IMEM_1D(465)
DEBUG memtool.phyinit.out_parser Write IMEM 1D as bin size 0x8000 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.bin
DEBUG memtool.phyinit.out_parser Write IMEM 1D as txt size 0x6eaf3 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.txt
DEBUG memtool.phyinit.out_parser Parse state PHASE.E_SET_DFI_CLOCK(16850)
DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1(16869)
DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1D(16885)
DEBUG memtool.phyinit.out_parser Write DMEM 1D as bin size 0x67c to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.bin
DEBUG memtool.phyinit.out_parser Write DMEM 1D as txt size 0x5398 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.txt
DEBUG memtool.phyinit.out_parser Parse state PHASE.G_EXEC_FW(17716)
DEBUG memtool.phyinit.out_parser Parse state PHASE.PHASE.I_LOAD_PIE(17782)
DEBUG memtool.phyinit.out_parser Write PIE as txt size 0x44ff to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.txt
DEBUG memtool.phyinit.out_parser Write PIE as txt size 0x933a to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.json
DEBUG memtool.phyinit.out_parser Parse state PHASE.H_READ_MSG_BLOCK(18389)
DEBUG memtool.phyinit.out_parser Parse retention register list
INFO memtool.comm.serial_channel Using serial: COM3
DEBUG memtool.common.factories new instance -> {inst}
DEBUG memtool.common.factories new instance -> {inst}
DEBUG memtool.common.factories new instance -> {inst}
DEBUG memtool.comm.serial_channel Channel is not alive
DEBUG spsdk.utils.interfaces.device.usb_device Closing the Interface: SE Blank 865 (0x1FC9, 0x0146)path=b'\\\\?\\hid#vid_1fc9&pid_0146#6&dc7bbf3&0&0000#{4d1e55b2-f16f-11cf-88cb-001111000030}' sn=''
DEBUG memtool.comm.serial_channel ==================hardware_init=======================
DEBUG memtool.comm.serial_channel
DEBUG memtool.comm.serial_channel [DEBUG]: Clock setup...
DEBUG memtool.comm.serial_channel [INFO]: ARM core clock rate is 1800MHz...
DEBUG memtool.comm.serial_channel [INFO]: DDR Dram frequency is 666MHz...
DEBUG memtool.comm.serial_channel [DEBUG]: Clock setup ended...
DEBUG memtool.comm.serial_channel ==================hardware_init exit==================
DEBUG memtool.comm.serial_channel
DEBUG memtool.comm.serial_channel
DEBUG memtool.comm.serial_channel
DEBUG memtool.comm.serial_channel
DEBUG memtool.comm.serial_channel Channel is alive
DEBUG memtool.comm.serial_channel Executing: mw92EAB8,1
DEBUG memtool.comm.serial_channel Result: 0x5588DCFE
INFO memtool.common.base_test Read app state WAIT_FOR_INPUT
INFO memtool.common.base_test Write app log level
DEBUG memtool.comm.serial_channel Executing: Mw92F510,1:0000000a
INFO memtool.common.base_test Write app state CONFIG_RECEIVED
DEBUG memtool.comm.serial_channel Executing: Mw92EAB8,1:55aa55aa
DEBUG test_app [DEBUG]: Initialize mailbox...
DEBUG test_app [DEBUG]: Apply Init PHY Config...
DEBUG test_app [DEBUG]: Execute PHY operation...
DEBUG test_app [DEBUG]: Run PHY full init...
DEBUG test_app [DEBUG]: Write 1D imem image, offset 0x00050000 size 0x00004000...
DEBUG test_app [DEBUG]: End of load 1D imem image...
DEBUG test_app [DEBUG]: Set DFI Clock for pstate 0...
DEBUG test_app [DEBUG]: Write 1D dmem image, offset 0x00054000 size 0x0000033e...
DEBUG test_app [DEBUG]: End of load 1D dmem image...
DEBUG test_app [INFO]: Execute Training Firmware for 1D pstate0@667MHz...
DEBUG test_app [INFO]: Training Firmware completed for 1D pstate0@667MHz with status 0; Execution ended in 0s.310ms.912us...
DEBUG test_app [DEBUG]: PHY operation ended with status 0...
DEBUG memtool.comm.serial_channel Executing: mw92F918,1
DEBUG memtool.comm.serial_channel Result: 0x00000000
DEBUG memtool.comm.serial_channel
DEBUG memtool.comm.serial_channel
DEBUG memtool.comm.serial_channel
DEBUG memtool.comm.serial_channel Channel is alive
DEBUG memtool.comm.serial_channel Executing: mw92EAB8,1
DEBUG memtool.comm.serial_channel Result: 0x5588DCFE
INFO memtool.common.base_test Read app state WAIT_FOR_INPUT
INFO memtool.common.base_test Read phy status
DEBUG memtool.comm.serial_channel Executing: mw92F91C,1
DEBUG memtool.comm.serial_channel Result: 0x00000059
INFO root Number of logged items 0x59
DEBUG memtool.memtests.snps_phy Using messages file C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\firmware\2020.06\lpddr4\lpddr4_pmu_train.strings
DEBUG memtool.memtests.snps_phy Using messages file C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\firmware\2020.06\lpddr4_2d\lpddr4_2d_pmu_train.strings
DEBUG memtool.comm.serial_channel Executing: mb961000,400
DEBUG memtool.comm.serial_channel Executing: mb961400,400
DEBUG memtool.comm.serial_channel Executing: mb961800,400
DEBUG memtool.comm.serial_channel Executing: mb961C00,400
DEBUG memtool.comm.serial_channel
DEBUG memtool.comm.serial_channel
DEBUG memtool.comm.serial_channel
DEBUG memtool.comm.serial_channel Channel is alive
DEBUG memtool.comm.serial_channel Executing: mw92EAB8,1
DEBUG memtool.comm.serial_channel Result: 0x5588DCFE
INFO memtool.common.base_test Read app state WAIT_FOR_INPUT
INFO memtool.common.base_test Write input param test = 200
DEBUG memtool.comm.serial_channel Executing: Mw92EA10,1:000000c8
INFO memtool.common.base_test Write app state INPUT_RECEIVED
DEBUG memtool.comm.serial_channel Executing: Mw92EAB8,1:77665544
DEBUG memtool.comm.serial_channel Executing: mw92EAB8,1
DEBUG memtool.comm.serial_channel Result: 0x5588DCFE
INFO memtool.common.base_test Read symbol app_state = 0x5588dcfe
DEBUG memtool.comm.serial_channel Executing: mw92EABC,1
DEBUG memtool.comm.serial_channel Result: 0x00000001
INFO memtool.common.base_test Read symbol num_records = 0x1
INFO memtool.common.base_test App state WAIT_FOR_INPUT
DEBUG memtool.comm.serial_channel Executing: mw92EF40,8
DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0]
INFO memtool.common.base_test Read symbol debug = [0, 0, 0, 0, 0, 0, 0, 0]
DEBUG memtool.comm.serial_channel Executing: mw92EF60,A
DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
INFO memtool.common.base_test Read symbol err_capt_regs = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
DEBUG memtool.comm.serial_channel Executing: mw92EF88,20
DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
INFO memtool.common.base_test Read symbol debug_regs = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
DEBUG memtool.comm.serial_channel Executing: mw92EAC0,1
DEBUG memtool.comm.serial_channel Result: 0x00000001
INFO memtool.common.base_test Read symbol state = 1
DEBUG memtool.comm.serial_channel Executing: mw92EAC4,1
DEBUG memtool.comm.serial_channel Result: 0x000000C8
INFO memtool.common.base_test Read symbol test_id = 200
INFO memtool.common.base_test Record 0 state TestStatus.PASS
DEBUG memtool.comm.serial_channel Executing: mw92EAC8,10
DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
INFO memtool.common.base_test Read test data [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
INFO memtool.common.base_test Test 200 finished with state 1
DEBUG memtool.common.base_test App state: WAIT_FOR_INPUT
DEBUG memtool.common.base_test Err_caption_registers: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
DEBUG memtool.common.base_test Debug: [0, 0, 0, 0, 0, 0, 0, 0]
DEBUG memtool.common.base_test Debug registers: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
DEBUG memtool.common.base_test Results: [{'state': 1, 'test_id': 200, 'data': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'}]
DEBUG memtool.common.base_test Number of records: 1
ERROR memtool.memtests.phy_diags_tests CA data is missing!
{'app_state': 1435032830, 'num_records': 1, 'records': [{'state': 1, 'test_id': 200, 'data': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'}], 'debug': '[0, 0, 0, 0, 0, 0, 0, 0]', 'err_capt_regs': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0]', 'debug_regs': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'}
****DONE****

"CA Eye" always runs into timeout, I tried different values for "ATXImpedance" and with value of 20Ohm it's able to run longer for about one cycle, but in the end it still times out. See the full log in the spoiler

Spoiler

#################### Result for: ca_eye ###### Run 1 ###############################################Microsoft Windows [Version 10.0.19045.2965]
(c) Microsoft Corporation. All rights reserved.

C:\nxp\i.MX_CFG_25.03\bin>prompt test-prefix :

test-prefix : "C:/nxp/i.MX_CFG_25.03/bin/python3/python" "C:/nxp/i.MX_CFG_25.03/bin/python3/memtool/memtool_entry.py" -t "runtest" -d "C:/ProgramData/NXP/mcu_data_25.03/processors/MIMX8ML8xxxKZ/ksdk2_0/mem_validation/ddrc" -p "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy_training_ca_eye_lpddr4_0_0_.log" -i "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/figure_ca_eye_lpddr4_0_0_.png" -l DEBUG "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/connect.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/test.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_registers.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config_in.json"
INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/connect.json
INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/test.json
INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy.json
INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_registers.json
INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config.json
INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config_in.json
DEBUG memtool.common.factories new instance -> {inst}
DEBUG memtool.processor.base_processor freq_0 set to 667
INFO memtool.phyinit.phy_init Run phyinit for 2020.06\lpddr4
DEBUG memtool.phyinit.phy_init Shared library C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\phyinit\sharedlib\phyinit_2020.06_lpddr4.dll
DEBUG memtool.common.factories new instance -> {inst}
DEBUG memtool.phyinit.phy_init PHY config file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_config_final.json
DEBUG memtool.phyinit.phy_init Phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txt
DEBUG memtool.phyinit.phy_init Retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txt
DEBUG memtool.phyinit.out_parser Parse phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txt
DEBUG memtool.phyinit.out_parser Parse retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txt
DEBUG memtool.phyinit.out_parser Parse state A_BRING_UP_POWER
DEBUG memtool.phyinit.out_parser Parse state C_PHY_INIT_CONFIG(210)
DEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x32fb to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.c
DEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x15d4 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.json
DEBUG memtool.phyinit.out_parser Parse state LOAD_IMEM_1(445)
DEBUG memtool.phyinit.out_parser Parse state D_LOAD_IMEM_1D(465)
DEBUG memtool.phyinit.out_parser Write IMEM 1D as bin size 0x8000 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.bin
DEBUG memtool.phyinit.out_parser Write IMEM 1D as txt size 0x6eaf3 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.txt
DEBUG memtool.phyinit.out_parser Parse state PHASE.E_SET_DFI_CLOCK(16850)
DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1(16869)
DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1D(16885)
DEBUG memtool.phyinit.out_parser Write DMEM 1D as bin size 0x67c to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.bin
DEBUG memtool.phyinit.out_parser Write DMEM 1D as txt size 0x5398 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.txt
DEBUG memtool.phyinit.out_parser Parse state PHASE.G_EXEC_FW(17716)
DEBUG memtool.phyinit.out_parser Parse state PHASE.PHASE.I_LOAD_PIE(17782)
DEBUG memtool.phyinit.out_parser Write PIE as txt size 0x44ff to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.txt
DEBUG memtool.phyinit.out_parser Write PIE as txt size 0x933a to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.json
DEBUG memtool.phyinit.out_parser Parse state PHASE.H_READ_MSG_BLOCK(18389)
DEBUG memtool.phyinit.out_parser Parse retention register list
INFO memtool.comm.serial_channel Using serial: COM3
DEBUG memtool.common.factories new instance -> {inst}
DEBUG memtool.common.factories new instance -> {inst}
DEBUG memtool.common.factories new instance -> {inst}
DEBUG memtool.comm.serial_channel
DEBUG memtool.comm.serial_channel
DEBUG memtool.comm.serial_channel
DEBUG memtool.comm.serial_channel Channel is alive
INFO memtool.comm.serial_channel Send reset to target
DEBUG memtool.comm.serial_channel Executing: R
DEBUG spsdk.utils.interfaces.device.usb_device Closing the Interface: SE Blank 865 (0x1FC9, 0x0146)path=b'\\\\?\\hid#vid_1fc9&pid_0146#6&dc7bbf3&0&0000#{4d1e55b2-f16f-11cf-88cb-001111000030}' sn=''
DEBUG memtool.comm.serial_channel ==================hardware_init=======================
DEBUG memtool.comm.serial_channel
DEBUG memtool.comm.serial_channel [DEBUG]: Clock setup...
DEBUG memtool.comm.serial_channel [INFO]: ARM core clock rate is 1800MHz...
DEBUG memtool.comm.serial_channel [INFO]: DDR Dram frequency is 666MHz...
DEBUG memtool.comm.serial_channel [DEBUG]: Clock setup ended...
DEBUG memtool.comm.serial_channel ==================hardware_init exit==================
DEBUG memtool.comm.serial_channel
DEBUG memtool.comm.serial_channel
DEBUG memtool.comm.serial_channel
DEBUG memtool.comm.serial_channel
DEBUG memtool.comm.serial_channel Channel is alive
DEBUG memtool.comm.serial_channel Executing: mw92EAB8,1
DEBUG memtool.comm.serial_channel Result: 0x5588DCFE
INFO memtool.common.base_test Read app state WAIT_FOR_INPUT
INFO memtool.common.base_test Write app log level
DEBUG memtool.comm.serial_channel Executing: Mw92F510,1:0000000a
INFO memtool.common.base_test Write app state CONFIG_RECEIVED
DEBUG memtool.comm.serial_channel Executing: Mw92EAB8,1:55aa55aa
DEBUG test_app [DEBUG]: Initialize mailbox...
DEBUG test_app [DEBUG]: Apply Init PHY Config...
DEBUG test_app [DEBUG]: Execute PHY operation...
DEBUG test_app [DEBUG]: Run PHY full init...
DEBUG test_app [DEBUG]: Write 1D imem image, offset 0x00050000 size 0x00004000...
DEBUG test_app [DEBUG]: End of load 1D imem image...
DEBUG test_app [DEBUG]: Set DFI Clock for pstate 0...
DEBUG test_app [DEBUG]: Write 1D dmem image, offset 0x00054000 size 0x0000033e...
DEBUG test_app [DEBUG]: End of load 1D dmem image...
DEBUG test_app [INFO]: Execute Training Firmware for 1D pstate0@667MHz...
DEBUG test_app [INFO]: Training Firmware completed for 1D pstate0@667MHz with status 0; Execution ended in 0s.310ms.898us...
DEBUG test_app [DEBUG]: PHY operation ended with status 0...
DEBUG memtool.comm.serial_channel Executing: mw92F918,1
DEBUG memtool.comm.serial_channel Result: 0x00000000
DEBUG memtool.comm.serial_channel
DEBUG memtool.comm.serial_channel
DEBUG memtool.comm.serial_channel
DEBUG memtool.comm.serial_channel Channel is alive
DEBUG memtool.comm.serial_channel Executing: mw92EAB8,1
DEBUG memtool.comm.serial_channel Result: 0x5588DCFE
INFO memtool.common.base_test Read app state WAIT_FOR_INPUT
INFO memtool.common.base_test Read phy status
DEBUG memtool.comm.serial_channel Executing: mw92F91C,1
DEBUG memtool.comm.serial_channel Result: 0x00000059
INFO root Number of logged items 0x59
DEBUG memtool.memtests.snps_phy Using messages file C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\firmware\2020.06\lpddr4\lpddr4_pmu_train.strings
DEBUG memtool.memtests.snps_phy Using messages file C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\firmware\2020.06\lpddr4_2d\lpddr4_2d_pmu_train.strings
DEBUG memtool.comm.serial_channel Executing: mb961000,400
DEBUG memtool.comm.serial_channel Executing: mb961400,400
DEBUG memtool.comm.serial_channel Executing: mb961800,400
DEBUG memtool.comm.serial_channel Executing: mb961C00,400
DEBUG memtool.comm.serial_channel
DEBUG memtool.comm.serial_channel
DEBUG memtool.comm.serial_channel
DEBUG memtool.comm.serial_channel Channel is alive
DEBUG memtool.comm.serial_channel Executing: mw92EAB8,1
DEBUG memtool.comm.serial_channel Result: 0x5588DCFE
INFO memtool.common.base_test Read app state WAIT_FOR_INPUT
INFO memtool.common.base_test Write input param test = 200
DEBUG memtool.comm.serial_channel Executing: Mw92EA10,1:000000c8
INFO memtool.common.base_test Write app state INPUT_RECEIVED
DEBUG memtool.comm.serial_channel Executing: Mw92EAB8,1:77665544
DEBUG memtool.comm.serial_channel Executing: mw92EAB8,1
DEBUG memtool.comm.serial_channel Result: 0x5588DCFE
INFO memtool.common.base_test Read symbol app_state = 0x5588dcfe
DEBUG memtool.comm.serial_channel Executing: mw92EABC,1
DEBUG memtool.comm.serial_channel Result: 0x00000001
INFO memtool.common.base_test Read symbol num_records = 0x1
INFO memtool.common.base_test App state WAIT_FOR_INPUT
DEBUG memtool.comm.serial_channel Executing: mw92EF40,8
DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0]
INFO memtool.common.base_test Read symbol debug = [0, 0, 0, 0, 0, 0, 0, 0]
DEBUG memtool.comm.serial_channel Executing: mw92EF60,A
DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
INFO memtool.common.base_test Read symbol err_capt_regs = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
DEBUG memtool.comm.serial_channel Executing: mw92EF88,20
DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
INFO memtool.common.base_test Read symbol debug_regs = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
DEBUG memtool.comm.serial_channel Executing: mw92EAC0,1
DEBUG memtool.comm.serial_channel Result: 0x00000001
INFO memtool.common.base_test Read symbol state = 1
DEBUG memtool.comm.serial_channel Executing: mw92EAC4,1
DEBUG memtool.comm.serial_channel Result: 0x000000C8
INFO memtool.common.base_test Read symbol test_id = 200
INFO memtool.common.base_test Record 0 state TestStatus.PASS
DEBUG memtool.comm.serial_channel Executing: mw92EAC8,10
DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
INFO memtool.common.base_test Read test data [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
INFO memtool.common.base_test Test 200 finished with state 1
DEBUG memtool.common.base_test App state: WAIT_FOR_INPUT
DEBUG memtool.common.base_test Err_caption_registers: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
DEBUG memtool.common.base_test Debug: [0, 0, 0, 0, 0, 0, 0, 0]
DEBUG memtool.common.base_test Debug registers: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
DEBUG memtool.common.base_test Results: [{'state': 1, 'test_id': 200, 'data': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'}]
DEBUG memtool.common.base_test Number of records: 1
DEBUG memtool.processor.base_processor freq_0 set to 667
DEBUG memtool.phyinit.phy_init PHY config file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_config_final.json
DEBUG memtool.phyinit.phy_init Phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txt
DEBUG memtool.phyinit.phy_init Retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txt
DEBUG memtool.phyinit.out_parser Parse phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txt
DEBUG memtool.phyinit.out_parser Parse retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txt
DEBUG memtool.phyinit.out_parser Parse state A_BRING_UP_POWER
DEBUG memtool.phyinit.out_parser Parse state C_PHY_INIT_CONFIG(210)
DEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x32fb to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.c
DEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x15d4 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.json
DEBUG memtool.phyinit.out_parser Parse state LOAD_IMEM_1(445)
DEBUG memtool.phyinit.out_parser Parse state D_LOAD_IMEM_1D(465)
DEBUG memtool.phyinit.out_parser Write IMEM 1D as bin size 0x8000 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.bin
DEBUG memtool.phyinit.out_parser Write IMEM 1D as txt size 0x6eaf3 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.txt
DEBUG memtool.phyinit.out_parser Parse state PHASE.E_SET_DFI_CLOCK(16850)
DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1(16869)
DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1D(16885)
DEBUG memtool.phyinit.out_parser Write DMEM 1D as bin size 0x67c to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.bin
DEBUG memtool.phyinit.out_parser Write DMEM 1D as txt size 0x5398 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.txt
DEBUG memtool.phyinit.out_parser Parse state PHASE.G_EXEC_FW(17716)
DEBUG memtool.phyinit.out_parser Parse state PHASE.PHASE.I_LOAD_PIE(17782)
DEBUG memtool.phyinit.out_parser Write PIE as txt size 0x44ff to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.txt
DEBUG memtool.phyinit.out_parser Write PIE as txt size 0x933a to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.json
DEBUG memtool.phyinit.out_parser Parse state PHASE.H_READ_MSG_BLOCK(18389)
DEBUG memtool.phyinit.out_parser Parse retention register list
DEBUG memtool.common.factories new instance -> {inst}
{'app_state': 1435032830, 'num_records': 1, 'records': [{'state': 1, 'test_id': 200, 'data': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'}], 'debug': '[0, 0, 0, 0, 0, 0, 0, 0]', 'err_capt_regs': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0]', 'debug_regs': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'}
DEBUG memtool.common.factories new instance -> {inst}
DEBUG memtool.comm.serial_channel
DEBUG memtool.comm.serial_channel
DEBUG memtool.comm.serial_channel
DEBUG memtool.comm.serial_channel Channel is alive
INFO memtool.comm.serial_channel Send reset to target
DEBUG memtool.comm.serial_channel Executing: R
ERROR libusbsio.hidapi.dev HID device 'b'\\\\?\\hid#vid_1fc9&pid_0146#6&dc7bbf3&0&0000#{4d1e55b2-f16f-11cf-88cb-001111000030}'' opening failed.
ERROR memtool.common.base_test Application load ended with exception: Download incomplete due to configuration error!
DEBUG memtool.comm.serial_channel Executing: mw92F918,1

[JorgeCas]

Hello,

The issue you are mentioning could be caused by marginal signal integrity or timing violations.

Please take a look in attached file for .alg file.

Best regards.

[sfatyushkin · Accepted solution]

Jorge, thanks a lot!
This helped us to understand the problem.
When laying out the LpDDR lines, we used the same rules as before when laying out iMX8MM, without paying attention to the tightening of the requirements for the CAx lines (within 2 ps in groups), and did not take into account the Pkg delay. So, two questions.
1. Is it possible to configure the CA_x_y lines and run the board with a spread of CA lines times of about 20 ps (possibly at a slow speed), or it is impossible to do without redesigning the board?
2. In the i.MX 8M Plus Hardware Developer’s Guide, all timings seems like in EVK. But the delay on the CK_A lines is indicated to be about 107 ps (145 ps taking into account the Pkg delay). On the EVK board (directly in the project that you provided), I see a delay on the CKa lines of about 89 ps (127 ps taking into account the Pkg delay, and this is outside the 50 ps tolerance for the CA_A_0...4 lines). What is correct?

Best regards,
Serge

[JorgeCas]

Hello,

1) A clock frequency reduction, but it is not a warranty that will work. 

2) It is under the recommendation, ±50 ps.

Best regards.

[sfatyushkin]

127 + 50 ps < 191ps

[JorgeCas]

Hello,

According to constraint manager, the routing is under the recommended values:

Best regards.

[sfatyushkin]

Hi Jorge,
1. Could you please provide the data on the chain lengths and propagation delays of LpDDR signals in EVK?
2. Our CAD does not allow importing the EVK pcb file in the format it is posted on your site. Can you provide it in ASCII format?

Best regards, Serge