I'm trying to configure the EQOS MAC for RMII connection with a TJA1102 phy on my custom i.MX8MP board. The PHY initialization looks correct, however, I always get the following error:
[ 7.823171] imx-dwmac 30bf0000.ethernet: Failed to reset the dma
[ 7.829205] imx-dwmac 30bf0000.ethernet eth1: stmmac_hw_setup: DMA engine initialization failed
[ 7.838562] imx-dwmac 30bf0000.ethernet eth1: stmmac_open: Hw setup failed
My device tree looks like this:
eqos: ethernet@30bf0000 {
compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
reg = <0x30bf0000 0x10000>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eth_wake_irq", "macirq";
clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
<&clk IMX8MP_CLK_QOS_ENET_ROOT>,
<&clk IMX8MP_CLK_ENET_QOS_TIMER>,
<&clk IMX8MP_CLK_ENET_QOS>;
clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
<&clk IMX8MP_CLK_ENET_QOS_TIMER>,
<&clk IMX8MP_CLK_ENET_QOS>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
<&clk IMX8MP_SYS_PLL2_100M>,
<&clk IMX8MP_SYS_PLL2_50M>;
assigned-clock-rates = <0>, <100000000>, <50000000>; // -> reconfigured to 50 MHz for RMII
nvmem-cells = <ð_mac2>;
nvmem-cell-names = "mac-address";
nvmem_macaddr_swap;
intf_mode = <&gpr 0x4>;
status = "disabled";
};
};&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rmii";
phy-handle = <ðphy1>;
/delete-property/ phy-supply;
status = "okay";
max-speed = <100>;
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
};
};
}; pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
MX8MP_IOMUXC_ENET_RD2__GPIO1_IO28 0x91
MX8MP_IOMUXC_ENET_RD3__GPIO1_IO29 0x91
MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 0x91
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12
MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x12
MX8MP_IOMUXC_ENET_TD3__GPIO1_IO18 0x1f
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12
MX8MP_IOMUXC_ENET_TXC__ENET_QOS_TX_ER 0x12
>;
};
I can see the 50 MHz clock output on the TD2 pad, but the rest of the RMII interface is doing nothing.
What am I missing?
In the reference manual I found the following remark:
Does this mean that there is anything else to do except setting the GPR_ENET_QOS_INTF_SEL field to RMII (which is done by dwmac-imx.c)?
I was able to resolve the issue by letting the PHY create the RMII ref clock. After adapting the dts (adding "snps,rmii_refclk_ext"), the DMA reset worked and I'm able to use the network interface as expected.
The only change is this bit in the IOMUX_GPR_GPR1 register:
Can someone please clarify why creating the clock directly (IMX8MP_SYS_PLL2_50M) does not work, but using an external clock works without a problem? When measured, both clocks looked valid (50 MHz).
