Hi,
Regarding the i.MX8M+ signals associated with LPDDR4 (DQ, DQS, CKE, etc.):
In the Hardware Development Guide, and also PEVK, all single ended signals are 50 Ohm, and differential signals are 85 Ohm.
I would expect the driver impedance (which I estimate on the order of 30 Ohm), the trace impedance, and the ODT to be the same impedance in order to prevent reflections.
The LPDDR4 memories can only provide On Die Terminations (ODT) of 40, 48, 60, 80, 120, or 240 Ohm.
So my questions are:
1. What is the ODT configured to the LPDDR4 on the IMX8M+ PEVK?
2. For differential signals, is the LPDDR4 memory's ODT single ended? By that I mean: Does the 85 Ohm differential actually sees two terminations?
3. What is the single ended impedance of the 85 Ohm differential? is it perhaps 40, or 48 Ohm?
4. Why use 50 Ohm single ended, and not 40 Ohm single ended, which matches the ODT?
5. I estimated the IMX8M+ Driver impedance, but is it actually calibrated to a specific value?
This is my first HW design with LPDDR4 and LVSTL, so if I'm lacking any basic information on the subject, please enlighten me.
Thank you.
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Hi,
Your options are rightfully identified, I'd add that the option 1 is an already tested option, that you can confirm working and validate at different speeds.
Option 2 and 3 are great options that would improve your design in terms of time or effectiveness, I agree with you that option 2 would need a new constraint for 40 ohm single ended signals but would be beneficial.
Nevertheless, customers are encouraged to explore their designs upon their needs, so, your best option is what you should go with,
Regards.
Hi,
Thank you for your interest in NXP Semiconductor products,
1. It's set to 6 (40 Ohm).
2. Two terminations.
3. This resource is useful.
4. In LPDDR4 design, it's accepted the adoption of 40 and 50 Ohm impedance.
5. It's calculated in the training stage of the boot process.
I also found an app note for DDR4 routing in LS processors that can help a little in this design stage.
Regards
Regards
Thank you, Joseph, your answers are very informative.
Unfortunately, it seems that the DDR4 routing recommendations is not very relevant, because it has a different termination scheme and different signaling.
For the 85 Ohm differential pair, I've put the stack up and trace dimensions in a calculator, which gives ~41 Ohm single ended impedance. (Attached image).
It looks like everything should be 40 Ohms: the driver is (probably) closer to 40 than 50, the ODT is chosen for 40 Ohm, and the differential 85 is built from two ~40 Ohm single ended.
If my understanding is correct, then I have 3 options:
1. Follow the recommendation as-is (85 differential, 50 Ohm single ended, 40 Ohm ODT).
2. Change the single ended signals to 40 Ohm.
3. Change the differential to 100 Ohm (= ~50 Ohm single ended), and use ODT of 48 Ohm.
It seems like the recommendation, option 1, is actually option 2, but with a compromise: using 50 Ohm single ended instead of 40 Ohm. possibly because it is already in the stack up.
If the many impedances in the stack up being the reason the recommendation is as it is, then maybe option 3 is preferred. There is already 100 Ohm differential for other signals (LVDS, etc.), and the 85 Ohm won't be necessary in the stack up.
I expect option 2 to be optimal in terms of signal integrity, because everything is matched to ~40 Ohm (single ended).
I'm currently leaning towards option 2: using 85 Ohm differential and 40 Ohm for single ended signals.
What do you think, Joseph?
Hi,
Your options are rightfully identified, I'd add that the option 1 is an already tested option, that you can confirm working and validate at different speeds.
Option 2 and 3 are great options that would improve your design in terms of time or effectiveness, I agree with you that option 2 would need a new constraint for 40 ohm single ended signals but would be beneficial.
Nevertheless, customers are encouraged to explore their designs upon their needs, so, your best option is what you should go with,
Regards.